高速存取

In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset.

在所述实施例中，响应于已经在第一可高速缓冲存储区域上复位加载/存储操作预留的判定，经由条件加载指令存取存储在第一可高速缓冲存储区域中的数据值。

The resulting system 1 maintains or improves CPU utilization rates as CPU speeds increase, 2 provides large level 1 caches while maintaining cache access times of one CPU clock cycle, and 3 provides high CPU utilization rates for those processing applications where locality of memory references is poor (e.g., networking applications).

随着CPU速度的提高，能够保持或提高CPU的利用率，2）提供大容量一级高速缓存，并同时保持高速缓存的存取时间为一个CPU时钟周期，3）为那些存储器引用局部性不强的处理系统提供高的CPU利用率。

By using this direct memory access transfer technology,system characters can be improved,CPU efficiency is enhanced and the difficulties of realizing the large high speed buffer are resolved.

利用DMA直接内存存取的数据传输技术，提高了系统性能，解放了CPU，解决了大量数据高速采集的问题。

The enhanced direct memory access is an important technology used for fast speed data transfer in data signal processor.EDMA is able to move data block independent of CPU, and this capability meets real-time image processing.

增强型直接内存存取是数字信号处理器中用于快速数据交换的重要技术，具有独立于CPU 的后台批量数据传输的能力，能够满足实时图像处理中高速数据传输的要求。

8 Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPUs execution load.

直接存储器存取使用为高速输出入装置为了避免增加CPU's 施行装载。a 。

The high capacity synchronous dynamic random access memory controlled by FPGA is used as the frame buffer of image data, thus solving the problems of the capacity and the speed in high resolution image data acquisition.

该方案中，由FPGA控制的高速大容量同步动态随机存储器作为图像数据的帧存，解决了高分辨率图像采集中容量和速度上的问题，SDRAM分时供FPGA和DSP访问的机制提高了数据存取的效率。

The high capacity synchronous dynamic random access memory controlled by FPGA is used as the frame buffer of image data, thus solving the problems of the capacity and the speed in high resolution image data acquisition. Sharing the SDRAM memory alternately by FPGA and DSP enhances the data access efficiency.

该方案中，由FPGA控制的高速大容量同步动态随机存储器作为图像数据的帧存，解决了高分辨率图像采集中容量和速度上的问题，SDRAM分时供FPGA和DSP访问的机制提高了数据存取的效率。

And we have given Hadamard matrix in detail in block design, coding and the specific application in communication., Hadamard code as a nonlinear combinatorial code has catered to the need of development of computer technology, stock systematic data and high speed for realizing and reliable access, request the error control code has not only little redundancy, but also can parallel encoding and decoding with high speed.

Hadamard码作为一种非线性组合码，迎合了计算机技术的发展对实现存储系统数据高速且可靠地存取，要求所采用的差错控制码不但冗余度小，还应当能高速并行编码和译码的需要。

System structure of the Neighborhood Image Frame Buffer is presented,aiming at the problem of the data stream of high speed image processing,especially the storing and accessing of the neighborhood image data.

本文针对高速图像处理的数据流问题，特别是邻域图像数据的并行存取问题，提出了邻域图像帧存储体的体系结构，实现了帧存储体邻域图像数据的并行存取，极大地提高了图像处理的速度。

We describe and compare five options for virtual address translation in the context of Distributed SharedMemory multiprocessors, including CC-NUMAs (Cache-Coherent Non-Uniform Memory Access Architectures) and COMAs (Cache Only Memory Access Architectures).

我们记录并对比了分布式共享内存多处理器环境下，包括CC-NUMAS(一致性高速缓存非均匀存储访问模型)和 COMA高速缓冲内存器存取模式）中的5个虚拟地址转换项目。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。