高速存储器

Each processor has its own caches,but they share the same global memory,disks and I/O devices.Only one copy of the operating system runs across all of the processors.

每一处理器都有自己的高速缓存，但它们共享相同的全局存储器、磁盘和I/O设备，仅有一个通过复制获得的操作系统在所有处理器间运行。

The research in the paper is based on digital signal processor, and focus on thesoftware and the hardware of the high speed memory test system.

本文以数字信号处理器为基础，详细分析、研究了高速测试存储器的软、硬件。

As a result, the development of networks is restricted severely. This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically.

提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题，理论上可以实现任意高速数据包的缓存。

A system for playing the digital video frequency with a changable playing back speed comprises: an acquiring module for acquiring the coded picture from the data memorizer; and a distributor module for selectively deleting the coded picture from the input high-speed buffer.

一种以变化的回放速度播放数字视频的系统可以包括：获取器模块，配置用于从数据存储器中获取编码后的画面；以及分配器模块，配置用于从输入高速缓冲器中选择性地删除编码后的画面。

The high speed multiplex first-in first-out storage structure includes at least two memory unit arrays, one integrated decoder circuit between the two memory unit arrays, one write-in control circuit over the decoder circuit, one read-out control circuit below the decoder circuit, two data buffers on the two memory unit arrays separately, two multiplex circuits and two output circuits below the two memory unit arrays separately, and one write-1 clock buffer and one read-out clock buffer over and below the decoder circuit separtely.

一种高速多路先进先出存储器结构，包括一至少两存储单元阵列、一位于至少两存储单元阵列中间的整体解码电路、分别位于整体解码电路的上下的一写入控制电路及一读出控制电路、分别位于至少两存储单元阵列上的两数据输入缓冲器以及依序位于两存储单元阵列下的两多工电路及两输出电路，在整体解码电路的上下分别设置一写入时钟缓冲器及一读出时钟缓冲器。

These memory access resources include cache resources, burst mode operation control and precharge operation control.

这些存储器存取源包括高速缓存源、突发数据组模式操作和预充电控制。

It's a clever technique to help a computer processor work more smoothly.

高速缓冲存储器是完全针对速度和效率的设计，它能帮助计算机更平稳的工作。

Traditional design ways already cant give a reliable solution for these systems, especially when DDR memories come into fact. High-end designers must pay special attention to the signal integrity problems.

尤其是随着DDR存储器等高速器件的诞生，传统的电路设计方法已经无法保证系统的可靠性，信号完整性分析已经成为高级电子设计人员非常关心的问题。

Furthermore, if one or more small data blocks accessed before exist among its corresponding large block of data to be expelled from the fully associative buffer, the small block accessed is copied to the direct-mapped cache.

而且，如果以前被访问的一个或多个小数据块，存在于它的将要从完全联系的缓冲器中挤出的相对应的大块数据之中，就将被访问的小块复制到直接映射的高速缓冲存储器中。

The cache freshing and flushing mechanism is designed differently by different vendors.

各个制造商对高速缓冲存储器溢出以及清空机制设计不同。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。