高速存储器

AppleTalk addresses are temporary addresses that are assigned dynamically from a pool, or cache.

AppleTalk地址属于临时地址，由一个高速缓冲存储器中动态分配。

The resulting system 1 maintains or improves CPU utilization rates as CPU speeds increase, 2 provides large level 1 caches while maintaining cache access times of one CPU clock cycle, and 3 provides high CPU utilization rates for those processing applications where locality of memory references is poor (e.g., networking applications).

随着CPU速度的提高，能够保持或提高CPU的利用率，2）提供大容量一级高速缓存，并同时保持高速缓存的存取时间为一个CPU时钟周期，3）为那些存储器引用局部性不强的处理系统提供高的CPU利用率。

But by high-speed static RAM buffer composition, structure more complex, in the CPU die area can not be the case too, L1 cache capacity level can not be done too.

不过高速缓冲存储器均由静态RAM组成，结构较复杂，在CPU管芯面积不能太大的情况下，L1级高速缓存的容量不可能做得太大。

But by high-speed static RAM buffer composition, structure more complex, in the CPU die area can not be the case too, L1 cache capacity level can not do too much, L1 cache capacity is generally KB .

不过高速缓冲存储器均由静态RAM组成，结构较复杂，在CPU管芯面积不能太大的情况下，L1级高速缓存的容量不可能做得太大，L1缓存的容量单位一般为KB。

The PNDC was not built, but work on it led Pomerene to the idea of making a highly available memory system out of a number of memory units, each storing one bit position of a word.

PNDC虽然只停留在设计阶段，没有实际建造，但它的一些思想，如包含高速缓冲存储器在内的多级存储器系统等，在以后的系统中获得了发展和使用。

Wait states can be eliminated—resulting in a "zero wait state" machine—by using fastcache memory ,interleaved memory ,page-mode RAM ,or static RAM chips.

通过使用快速的高速缓冲存储器、交错存取存储器、页面式RAM或静态RAM芯片，等待状态可消除，从而产生"零等待状态"机。

Speed of memory .Wait states can be eliminated-resulting in a "zero wait state" machine-by using fastcache memory ,interleaved memory ,page-mode RAM ,or static RAM chips.

通过使用快速的高速缓冲存储器、交错存取存储器、页面式RAM或静态RAM芯片，等待状态可消除，从而产生"零等待状态"机。

Wait states can be eliminatedresulting in a "zero wait state" machineby using fastcache memory ,interleaved memory ,page-mode RAM ,or static RAM chips.

通过使用快速的高速缓冲存储器、交错存取存储器、页面式RAM或静态RAM芯片，等待状态可消除，从而产生"零等待状态"机。

In the context of COMAs, the allocation of pages to processor nodes is not as critical because memory blocks can dynamically migrate and replicate freely among nodes.

在高速缓冲存储器存取模式中，中央处理器节点的页面配置并非至关重要的，因为存储器可以在节点中自由转移和复制。

Four 8-bit I/O Ports C Three 16-bit Timer/Counters C 256 Bytes Scratch Pad RAM C 8 Interrupt Sources with 4 Priority Levels C Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals High-speed Architecture C 10 to 40 MHz in Standard Mode 16K/32K Bytes On-Chip ROM Program T80C51RD2 ROMless Versions On-Chip 1024 bytes Expanded RAM C Software Selectable Size (0, 256, 512, 768, 1024 bytes) C 256 Bytes Selected at Reset for AT87C51RB2/RC2 Compatibility Keyboard Interrupt Interface on Port P1 8-bit Clock Prescaler 64K Program and Data Memory Spaces Improved X2 Mode with Independant Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels with: C High-speed Output C Compare/Capture C Pulse Width Modulator C Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes C Idle Mode C Power-down Mode C Power-off Flag Power Supply: 2.7V to 5.5V or 2.7V to 3.6V Temperature Ranges: Commercial (0 to +70C) and Industrial (-40C to +85C) Packages: PDIL40, PLCC44, VQFP44

四8位I / O端口C款三16位定时器/计数器 256字节RAM的便笺簿 8中断源4优先级和C双数据指针MOVX在缓变长内存/外设高速架构为C 10至40 MHz的标准模式16K/32K字节的片上ROM程序T80C51RD2无ROM版本片1024字节扩展RAMC软件可选尺寸（0，256， 512，768，1024字节）C选取在重置为AT87C51RB2/RC2兼容键盘中断接口与独立的选择港口小一8位时钟分频器64K的程序和数据存储器空间的改进X2模式的CPU和256字节每个外设可编程计数器5通道的阵列：C型高速输出C比较/脉宽调制器捕获看门狗定时器复位功能异步端口全双工增强型UART的波特率发生器的UART低EMI硬件看门狗定时器电源控制模式空闲模式C掉电模式C断电旗电源：2.7V至5.5V或2.7V至3.6V温度范围：商业（0到+70 C）和工业（- 40C至+85℃）封装：PDIL40，PLCC44，VQFP44

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。