高速存储器

If the destination IP address is local ,the router searches an internal store of IP addresses and local－device Media Access Control addresses. This store is known as the Address Resolution Protocol cache.

如果目的IP地址为本地的，该路由器就搜寻存储着IP地址和本地设备介质访问控制地址的内部存储器，这个存储器叫作地址分辨协议高速缓存。

One known principle utilizes a bank of arithmetic elements working in a pipeline and connected to local fast memories and to a bulk storage.

一种 已知的原理利用一组以管道方式工作，并联接到本地高速存储器和一个海量存储器的算术单元。

The scanner in MOTOROLA at the core of DSP56F826 using CMOS image sensor with progressive scan bar code data collection methods and to expand the use of high-speed memory chips, as well as sophisticated decoding algorithms, implementation of a highly efficient and accurate real-time processing.

该扫描器以MOTOROLA的DSP56F826为核心，采用CMOS图象传感器以逐行扫描方式采集条码数据，并利用高速存储器扩展芯片，配合先进的译码算法，实现了高效准确的实时处理。

If the destination IP address is local, the router searches an internal store of IP addresses and local－device Media Access Controladdresses. This store is known as the Address Resolution Protocolcache.

假如目的IP地址为本地的，该路由器就搜寻存储着IP地址和本地设备介质访问控制地址的内部存储器，这个存储器叫作地址分辨协议高速缓存。

Some techniques, such as multiprocessor organization, pipeline, virtual memory, ring-protection of main memory, multiple memory modules with address interleaving, cache, RAS and 1/O standard interface, have been employed in the system. A simple form of single-arm-latch has been adopted. Operating system used in HDS-9 is symmetric to each processor.

此机在系统结构上采用多重处理机结构，流水线控制技术，虚拟存储器技术，存储器环状保护技术，存储器多模交叉访问，高速缓冲技术，RAS技术，统一标准接口的I/O系统；在工艺技术方面采用高密度组装技术，用SSI-TTL电路组成单臂门闩触发器系统；在系统软件方面采用匀称或平等的操作系统来处理多重处理机关系。

Some techniques, such as multiprocessor organization, pipeline, virtual memory, ring-protection of main memory, multiple memory modules with address interleaving, cache, RAS and 1/O standard interface , have been employed in the system. A simple form of single-arm-latch has been adopted.

此机在系统结构上采用多重处理机结构，流水线控制技术，虚拟存储器技术，存储器环状保护技术，存储器多模交叉访问，高速缓冲技术，RAS技术，统一标准接口的I/O系统；在工艺技术方面采用高密度组装技术，用SSI-TTL电路组成单臂门闩触发器系统；在系统软件方面采用匀称或平等的操作系统来处理多重处理机关系。

This high-speed element is used as a "scratch pad" to temporarily store data and instructions that are likely to be retrieved many times during processing.Processing speed can thus be improved.Data may be transferred automatically between the buffer and primary storage so that the buffer is usually invisible to the application programmer.Once found only in large systems,cache memory is now avaliable in some of the tiny microprocessor chips used in personal computers.

该高速存储器可用作"便笺"，暂时存放那些在处理中很可能多次查询的数据和指令，这样可提高处理速度，由于数据在这个高速缓冲器和主存之间可自动传输，所以该告诉缓冲存储器对应用程序员来讲通常是不可见的，过去只在较大的计算机系统中才有的高速缓冲存储器，现在在一些用于个人计算机系统的很小的微处理器芯片中也采用了。

According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory.

根据一个实施例，数据处理系统中一致性管理的方法包括：在处于独占所有权一致性状态的较高级别高速缓存存储器中保存高速缓存线，以及其后从较高级别高速缓存存储器移除高速缓存线，并且从较高级别高速缓存存储器发送对高速缓存线的掷出请求到较低级别高速缓存存储器。

TOP414GN Pinout: Hynix HYMD232726A8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules which are organized as 32Mx72 high-speed memory arrays.

TOP414GN引脚说明：现代HYMD232726A的8-M/K/H/L系列缓冲184针双数据速率同步DRAM双列内存模组，其中为32Mx72高速存储器阵列举办。

MAX489CSD Pinout: Hynix MAX489CSD-H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Mod- ules which are organized as 32Mx64 high-speed memory arrays.

MAX489CSD引脚说明：海力士MAX489CSD -的H / L系列是缓冲184针双数据速率同步DRAM双列内存国防部- ules的是为32Mx64高速存储器阵列举办。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。