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ISM64×64-3 works in the same mode as ISM64×64-2, but was added one sample and hold circuit.

ISM64×64-3型电路仍然采用直接注入读出模式,行积分工作,但是增加了一级采样保持电路。

The circuit utilizes charge redistribution technique and consists of analog function blocks such as operational amplifier with feedback, sample and hold circuit and logic discrimination circuit, etc.

该混沌函数以电压作为迭代变量,电路采用了负反馈形式的运放、采样保持电路和逻辑判断电路等模块,并运用了电荷再分配技术。

In the course of developing the hardware system, the circuits diagram is finished by the mean of EDA software. On the basis of analyzing function of hardware circuit, choose the AT89C51 as single chip microprocessor. Filter and amplifier circuit, sample and hold circuit, Analog-to-Digital conversion circuit, watchdog circuit, out port control circuit and power supply circuit were designed.

在硬件系统研制过程中,应用EDA软件完成电路原理图的设计,分析了硬件系统的各个组成部分及其功能,选用ATMEL公司的AT89C51单片机作为微处理器,设计了滤波放大电路、采样/保持电路、A/D转换电路、看门狗电路、输出控制电路以及电源电路。

Detailly,signals of background magnetic field is filtered by fixed frequency of sample and hold circuit which is supplied by logic circuit,and the signals before objects appear are tracked dynamically which are then compared with the ones after objects appear by comparator circuit,in order to furthest obtain the signals of target magnetic field on the basis of background magnetic field compensation.

运用逻辑脉冲电路为采样保持电路提供固定频率滤除背景磁场信号,并对目标未出现时的信号进行动态跟踪,运用比较电路将目标出现前后的信号进行比较,从而在补偿背景磁场的基础上最大限度地获得目标磁场的信号。

In the system, a finepositioning window signal generating circuit redundant, sample and hold circuit of positioning error signal using no traditional charge/discharge method but high-speed switches and operational amplifier integrators, and cross-zero detector with threshold for higher reliability, is originated by the author in this paper.

综合面伺服和扇区伺服的各自优点,设计完成了4000 TPI光刻伺服解调系统:在设计中,首创了带冗余的精定位窗口信号生成电路,采用高速模拟开关和运放积分电路代替传统的电容充放电法,以完成精定位位置误差信号的平均与采样保持,使用带阈值的过零检测电路提高过道脉冲的可靠性。

To reduce the area of the layout,we use one-stage OP-AMP in the ROIC,and the sample and hold circuit shared by pixels in a column is also applied instead of sample and hold circuit in every pixel.

本设计采用电容反馈互阻抗放大器结构作为输入级,列共用方式的采样保持电路,源级跟随器作为输出级,用移位寄存器来控制行、列选通并控制电路工作的时序。

With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit and the sub-stages.

同时利用增益增强技术设计高直流增益和高单位增益带宽的运放,从而保证采样保持电路和子级电路的性能。

Considering the speed , power dissipation and specifications, A flip-around sample and hold circuit was designed to reduce the power consumption; S/H circuit is followed by eight 1.5-bit stages and a final 2-bit flash sub-ADC.

该流水线式ADC的采样保持电路采用Flip-around结构以减少功耗;前8级每级1.5位,最后一级为2位的并行flash ADC,并采用数字校正技术对级电路的误差进行校正,最终以达到10位的精度;为了达到系统低功耗的要求,该流水线ADC采用了运放共享技术和逐级缩小技术。

Image analysis ; Histogram ; Real-time analysis ; Correlation coefficient ; Sample

图像分析;直方图;实时分析;相关系数;采样

The algorithm reduces the dimension of the input vectors by using the Toeplitz technique for the sample correlation matrix and needs only the first column of the processed matrix.

该算法仅将Toeplitz化后的采样协方差矩阵的第一列元素作为网络输入,从而降低了输入矢量的维数。

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