逻辑移位

Arithmetic and logic unit which performs arithmetic, logical, and shift operations to produce results.

算术逻辑单元，执行算术运算，逻辑运算和移位操作并生成结果； 3。

The biconditional markers placed on the rail track are detected sequentially by the on-board reader, and checked by the feedback logic function of generating absolute position encoding sequence.

当列车在线路上运行时，通过车载阅读器顺序检测二值标记，在移位存储器中构成绝对位置编码值，利用生成绝对位置编码序列的反馈逻辑函数进行容错处理，输出定位信息。

The biconditional markers placed on the rail track are detected sequentially by the on-board reader, and checked by the feedback logic function of generating absolute position encoding sequence. The exclusive position code consists of the binary information in the shift register.

当列车在线路上运行时，通过车载阅读器顺序检测二值标记，在移位存储器中构成绝对位置编码值，利用生成绝对位置编码序列的反馈逻辑函数进行容错处理，输出定位信息。

The shift register is a sequential logical circuit, which can store and shift binary digit information.

移位寄存器是用来寄存二进制数字信息，并能将存储的信息移位的时序逻辑电路。

Serial Data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the CLOCK input pulse.

在串行数据输入端转移到了移位寄存器的逻辑0到逻辑1的时钟输入脉冲过渡。

Then, on the basis of the functional verification, the system architectures of the radio frequency analog front end and the control logic circuit for the passive UHF RFID transponder are studied and designed with low-power design techniques. The RF AFE circuit includes rectifier, matching network, backscatter, regulator, AM demodulator, voltage reference, local oscillator and power on reset circuit, and so on. The control logic circuit contains clock synchronization module, decoding module, coding module, cyclic redundancy checksum module, power management unit, control unit, shift register and memory.

然后，在功能验证的基础上，重点研究了无源超高频射频识别标签芯片射频模拟前端电路和控制逻辑电路的系统架构，并采用低功耗设计技术对其进行了设计，射频模拟前端电路设计包括了整流器、匹配网络、反向散射电路、稳压器、AM解调器、电压参考源、本地振荡器以及上电复位电路等，控制逻辑电路设计包括了时钟同步模块、解码模块、编码模块、CRC校验模块、功率管理单元、控制单元、移位寄存器和存储器等。

The algorithm is efficiently length-reduced compared with the traditional ones. It uses bitwise operation and shift logical for data substitution, and generates a length-fixed MAC.

算法通过位运算和逻辑移位进行数据替换，从而得到与验证的数据长度无关的定长MAC，有效减小了MAC的数据传输量。

Since for the detection of an asynchronous mode it is not important in what zone is Z, at the given moment but in what order and with what speed it passes these zones, a 16-digit word is formed, in which current CSMD values are recorded in turn at the moment of transition of Z, from one zone to another (before recording CSMD in rightmost positions of the word there is a logical shift to the left by three positions).

因为对于异步方式的检测来说，重要的并不是哪个区域是 Z ，而是在特定时刻它按什么顺序和以什么速度通过这些区域，16位字形成了，用16位字依次记录 Z 变化时刻的当前 CSMD 值，从一个区域到另一个(在字的最右位记录 CSMD 值之前应向左面逻辑移位三个位置)。

Common uses for the PLD include chip selects for external devices, state-machines, simple shifters and counters, key- pad and control panel interfaces, clock dividers, handshake delay, multiplexers, etc. This elimi- nates the need for small external PLDs and logic devices.

为共同使用的PLD芯片包括外部设备选择，状态机，简单的移位寄存器和计数器，关键垫和控制面板接口，时钟分频器，握手延迟，多路复用器，等这隐去，纳茨为小和外部需求的PLD逻辑器件。

The measured object can be found within a few milliseconds in the raster-scan image. 4 . Two lines delay for the processed image is implemented using two 128×8 shift registers with the configurable logic block in FPGA. A new fully pipelined bit parallel hardware architecture for Sobel edge detection is implemented with FPGA. Furthermore, it takes no more than 2ms to complete the edge detection of an image with 128×128 pixels.

视觉检测信号的前端处理技术 1、系统地分析了视觉检测算法层次性特点和计算特点，提出了提高视觉检测信号处理速度的基本方案：采用前端处理系统，自动识别被测物体在获取图像中的位置，并将真正有用的被测物体的边缘坐标值，提供给计算机，作进一步的高精度处理； 2、系统研究了实时图像硬件处理的设计基本方法，提出了基于FPGA的视觉检测信号的低级处理算法硬件实现模块化模型； 3、提出了一种新的基于FPGA的模板匹配并行模块化结构，解决了二维图像处理高带宽要求，在几毫秒内就可以在按扫描顺序输入图像中找到检测目标物体的位置； 4、采用FPGA内部的可配置逻辑块实现了128×8移位寄存器的设计，解决了大容量移位寄存器与FPGA内部寄存器数量之间的矛盾，实现了两行图像的延迟。

Neither the killing of Mr Zarqawi nor any breakthrough on the political front will stop the insurgency and the fratricidal murders in their tracks.

在对危险的南部地区访问时，他斥责什叶派民兵领导人对中央集权的挑衅行为。

In fact,I've got him on the satellite mobile right now.

实际上 我们已接通卫星可视电话了