逻辑电平

A use of task and level-sensitive always block design compared the reorganization of the signal combinational logic example.

详细说明：一个利用task和电平敏感的always块设计比较后重组信号的组合逻辑的实例。

A logic 1 output level results in a high impedance condition.

输出高电平逻辑1将会使得输出端为高阻状态。

After the UP and DN signals both become a logic high at the same time, NAND gate 403 generates a falling edge on VIN.

在UP和DN信号同时都变为逻辑高电平后，NAND门403产生VIN的下降沿。

After the UP and DN signals transition to a logic low, NAND gate 403 generates a rising edge in VIN, and pulse width generator 404 generates a rising edge in VOUT a delayed period of time later.

在UP和DN信号转换到逻辑低电平后，NAND门403在VIN中生成上升沿，且脉冲宽度发生器404在延迟时间段后在VOUT中生成上升沿。

When either NAND gate pulls low, the SLO state overrides the WHI state from the resistor and the net state is resolved to be logic low.

当与非门的任何一个输入电平为低时，SLO状态通过电阻R1克服WHI状态，使得最后的状态为逻辑低电平。

In digital circuitry a circuit, which recognizes a high level to be a logical 1 and a low level as a logical-0 is said to use positive logic .

在数字电路中，每个将高电平识别为逻辑 l。把低电平识别为逻辑0的电路，被称为使用正逻辑。

If the true ("1") level is the most positiv e voltage, this logic is referred to as positive true or positive logic.

如果真("1")电平是高的正电压，则此逻辑称为正逻辑。

74LS47N Pinout: The voltage at the TUNDER pin is equal to a logic-low level if the sensor detects a temperature that is less than the factory-programmed threshold temperature.

74LS47N引脚说明：在TUNDER引脚的电压等于逻辑低电平如果传感器检测到的温度是比工厂编程的起点温度低。

The most common exceptions to the use of the absolute magnitude convention are temperature and LOGIC levels.

绝对参量公约中最常见的例外就是温度和逻辑电平。

I can not make it blossom and suits me

我不能让树为我开花

When temperatures are above approximately 80 °C discolouration of the raceways or rolling elements is a frequent feature.

当温度高于 80 °C 左右时，滚道或滚动元件褪色是很常见的特征。