输入信号

It shows in the test of simulation sample that the ratio of interference inhibition is higher than 5000, and the minimum detected discharge magnitude is 0.06pC. Again, a method of polarity discrimination and high interference inhibition for the dual-input and single-output damped oscillation signal is proposed firstly.

在脉冲鉴别法的基础上，通过详细分析脉冲鉴别的原理和双端输入、单端输出信号的极性，首次提出了对双端输入、单端输出衰减振荡的局部放电信号进行极性鉴别的方法和极大干扰信号抑制方法。

If you wish to compress a particular track of a multitrack recording or one channel of a live performance, connect the 166XL INPUT to the audio source's output jack while the 166XL OUTPUT can be directly connected to a line input jack or the 166XL's INPUT and OUTPUT can be wired to an Insert point. In the latter case, the signals will most likely be unbalanced.

如果你希望压缩一个特殊的多音轨录音的轨迹或一个实时演奏的声道，可连接166XL的输入端口到音源的输出端口，同时166XL输出直接连接到一个线性输入接口，或166XL的输入输出连接到一个插口点，在后来的事例中，信号大多数像非平衡式信号。

The controller receives, analyzes and processes the command input by operator via the man-machine interface, to adjust and control the controllable light signal generator according to the analysis processing result and the spectrum result checked by the light checker, the controller outputs the adjustment and result via the man-machine interface to the operator, to output light signal for the result of adjustment and control on the controllable light signal generator, via the light coupler to be coupled partly and feedback to the light checker to be checked, thereby forming a closed-circuit, while the light signal coupled to the light output via the light coupler reaches user target spectrum demand.

本发明公开了一种实现光信噪比可调节的光信号源装置及控制方法，所述装置包括：控制器、人机接口、可控光信号发生器、光耦合器、光信号检测器、光信号输出口；控制器接收操作者输入给人机接口的指令并分析和处理，运用分析处理结果、并结合光检测器检测的光谱结果数据来调节和控制可控光信号发生器，控制器将调节过程和调节结果通过人机接口输出给操作者，对可控光信号发生器调节和控制的结果输出光信号通过光耦合器耦合一部分又反馈给光检测器检测，这样形成一个闭环控制，使得通过光耦合器耦合到光输出口的光信号达到用户目标光谱要求。

We designed the multi-channel delay and pulse adjustment circuit based on CPLD providing a solution to fast gating timing and delay problems in large nuclear physic experiments. Its main function is accepting a negative NIM trigger input, and outputting a pulse with adjustable delay and width. Minimum step accuracy of the delay and the pulse adjustment is 10ns when the system frequency is 100MHz.

针对大型核物理实验中的符合测量、多路时间测量系统中的门控快定时信号等应用的需要，设计了一种多路延迟／脉宽调节电路，主要功能是对输入的多路快信号进行延迟和脉宽调节，支持NIM负信号输入和输出，在系统主时钟频率为100MHz的时候，延迟和脉宽调节的最小步进精度为10ns。

The system comprises first and second antennas for receiving first and second RF signals of first and second frequencies, respectively; a mobile switch for measuring performance characteristics of the second antenna; and a switch circuit connected between the second antenna and the mobile switch for controlling flow of the first RF signal to the second antenna.

在移动通信终端内，一开关电路，用于根据工作模式控制CDMA天线的输入阻抗，该开关电路被连接在CDMA天线和移动开关之间，以便在GPS工作模式下维持CDMA天线的输入阻抗为高阻抗，来切断GPS信号的流入，以及在CDMA工作模式下维持CDMA天线的输入阻抗为低阻抗以接收CDMA信号。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

A device (ESF1) for spectral shaping of a discrete value transmission signal in a radio transmitter comprises one input (E1) for receiving an in phase component of the transmission signal and a further input (E2) for receiving a quadrature component of the transmission signal.

一种用于在无线发射机内对数值离散的发射信号进行频谱整形的装置(ESF1)，它具有一个用于接收所述发射信号的同相分量的第一输入端(E1)和一个用于接收所述发射信号的正交分量的第二输入端(E2)。

The first mixer input (44) is connected to the main input (50) and the first local oscillator input (47) is connected to a source that provides a first local oscillator signal (LO1) having a frequency omiga

第一混频器输入(44)连接到主输入(50)并且第一本地振荡器输入(47)连接到提供具有频率的第一本地振荡器信号(LO1)的信号源。

An image display apparatus includes a display having data holding function, a vertical drive circuit sequentially and selectively scanning matrix form display elements, and a horizontal drive circuit writing a voltage among binary voltage preliminarily assigned depending upon the digital data of the image signal. The horizontal drive circuit and the vertical drive circuit are operated for performing selective scan of respective display element for at least m times in one frame period. The vertical drive circuit is constituted of n number of sequence circuits and logic operation circuits for outputs of the sequence circuits, where n is smaller than m, a period from inputting to the sequence circuit to outputting from the final stage being less than or equal to half of one frame period, and at least one of the sequence circuits being used with selectively inputting a plurality of inputs.

提供了一种图象显示器，其具有显示部，在矩阵上排列的象素内保有数据保持的功能，根据保持的数据进行显示；垂直驱动电路，对构成显示部的矩阵状显示器以每行按顺序作选择性扫描；以及水平驱动电路，对于由垂直驱动电路选择的行显示器件，根据应显示的图象信号数字数据，从预先分配的二进制电压中写入电压，并利用水平、垂直驱动电路，与应显示的图象信号同步，在1帧期间至少m次对各显示象素进行选择性操作，以此进行多色调显示，垂直驱动电路由满足n＜m的n个顺序电路和其输出的逻辑运算电路组成，顺序电路的输入从最后级输出为止的期间为1帧期间的1/2以下，并且，n个顺序电路的至少一个的输入是切换多个输入系统而使用。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。