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A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock.

在发出每一个解串时钟后的预定的时间量之后,产生延迟的时钟脉冲。

The circuit encoding, data serialized methods and construction in the fiber transmission system are briefly described. The multiplex/demultiplex of parallel data and their different encoding function were realized by choosing a serializer/deserializer circuit with parallel input.

简述了光纤传输中线路编码、数据串行化的方法和构成,通过选择一种大位宽的串行器/解串行器电路,实现并行数据的复用/解复用以及不同的编码功能。

However, the Deserializer can lock to random data, which is discussed in the next section.

然而,解串器可以锁定随机数据,这在下一节讨论。

It is assumed that all code necessary for deserialization of a type is available for the deserializer to load.

大会加载。据推测,所有代码的反序列化的类型必须是为解串器可装载。

When the Deserializer synchronizes to the Serializer, the LOCK pin is low.

当同步的串行解串器,锁定引脚是低。

The serializer and deserializer use the power-down state, a low-power sleep mode, to reduce power consumption.

串行解串器的使用电源关闭状态,低功耗的睡眠模式,以减少电力消耗。

The serial interface uses LVDS Serializer and Deserializer technology.

串行接口使用的LVDS串行器及解串器的技术。

Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle.

请注意,区域管理小组模式不仅影响解串器锁定时间,而一旦解串器在锁,管理小组的模式,不影响解串器的状态,只要发生了相同的数据边界每个周期。

The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer.

1第1页,本页显示记录1-1,共1条记录分1页显示初始化并在其各自的章节中描述再同步方法是最快的方式建立之间的串行器及解串器的联系。

TA7366 Pinout: When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low.

TA7366引脚说明:当解串器锁相环锁定到嵌入式时钟边缘,解串器锁销声称低。

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