组合逻辑

Never gate your clock signal with combinational logic.

绝不使用组合逻辑控制时钟信号。

In synthesis, the cost of router with GLCA is only larger than that with RR by 25.7% in combinational logic.

综合结果显示， GLCA与RR方法相比，路由器仅在组合逻辑上有少许增加(25.7%)。

State machine was made up of register of status and combinational logic circuit. The status can be transferred as presetting before according to control signal. It is the control center of adjust relative action of signal to finish special operation.

状态机由状态寄存器和组合逻辑电路构成，能够根据控制信号按照预先设定的状态进行状态转移，是协调相关信号动作，完成特定操作的控制中心。

Conventional test generation algorithms for combinational logic circuits make use of backtracking during the search, that results in lowering down their running efficiency.

摘 要：传统的组合逻辑电路测试方法在搜索过程中都不可避免地要进行反向回溯，由于反向回溯的次数过多，往往会降低算法的效率。

MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.

详细说明：多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。

Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of ClassicEPGlO chip of Altera Co. and the detailed analyses of typical examples are also given.

结合Altera公司ClassicEP610芯片的结构，研究了将演化算法应用于函数级数字组合逻辑电路的硬件演化，并且对典型实例进行了详细分析。

This design which is based on the WindowsXp platform, using Graphic editor and text editor of MAX+PLUS II, to design Linear block code through VHDL and Combinational logic. both of these realization are simulated.

本设计基于windows xp平台，采用MAX + Plus II软件中的图形编辑模块和文本编辑模块，运用VHDL对线性分组编码器的编码功能，进行组合逻辑电路设计以及VHDL设计，并对两种设计进行波形仿真。

In this dissertation, we develop several power estimation and power modeling methods for combinational IPs.

在这篇论文中，我们针对组合逻辑电路的矽智产单元提出了一系列的功率消耗估测方法及功率消耗模型。

Treated as a synchronous datapath, the 4 phase bundled-data pipeline can be compiled top-down and with timing constraints. The full-custom C-elements are used in it and regarded as combinatorial gates during timing analysis. Circuit synthesized using this methodology will be better.

通过将4相位捆绑数据寄存器流水线数据通道等效为一个同步流水线，可以自顶向下地进行有时序约束的综合，采用全定制C单元，并把其当作组合逻辑门进行分析，综合出的电路更加优化。

A method for combinatory logic electric circuit fault detection based on feature analysis is introduced. And applies this method to the sequence circuit.

介绍了常用于组合逻辑电路故障检测的特征分析法，并将这种方法应用于时序电路。

On the other hand, the more important thing is because the urban housing is a kind of heterogeneity products.

另一方面，更重要的是由于城市住房是一种异质性产品。

Climate histogram is the fall that collects place measure calm value, cent serves as cross axle for a few equal interval, the area that the frequency that the value appears according to place is accumulated and becomes will be determined inside each interval, discharge the graph that rise with post, also be called histogram.

气候直方图是将所收集的降水量测定值，分为几个相等的区间作为横轴，并将各区间内所测定值依所出现的次数累积而成的面积，用柱子排起来的图形，也叫做柱状图。