硬件语言

In this thesis, algorithms and hardware implementations are studied on the vocoder system based on the Sinusoidal Model. After combining the phonetic classification algorithm with the Sinusoidal Model and taking advantage of the speech properties in Mandarin, good results are achieved.

本文对基于正弦模型的声码器系统从算法和硬件实现两方面进行了研究，将分类算法与正弦模型相结合，并利用汉语的语言特点，取得了比较理想的结果。

It uses logical program design language PROLOG as its hemal, and directly completes tasks described by PROLOG with harclware anal software.

它以逻辑程序设计语言PROLOG为核心，以硬件、软件两方面结合的方式直接实现以PROLOG所描述的推理任

C++ also supports several inherently nonportable features including bit-fields and volatile, which make it easier to interface to hardware, and linkage directives, which make it easier to interface to programs written in other langauges.

C++ 还支持几种固有的不可移植的特征，包括位域和 volatile（它们可使与硬件接口更容易）以及链接指示（它使得与用其他语言编写的程序接口更容易）。

Methods With AT89C51 single-chip as hardware and programmed by C language, the instrument applied, the optometer adopted LCD and international standard optotype. The optotype had 14 lines of object-finders, and only one line of random characters was displayed on the screen every time.

硬件采用AT89C51型单片机，软件采用C语言编程，显示部分采用液晶显示，以国际标准视力表&E&字为视标，视标共14行，每屏显示1行，随机显示字符，视力检查距离为3m，全部程序在单片机控制下完成。

Secondly, on the condition of understanding the PCI norm, we analyze the PCI time sequence and address configuration space etc. detailedly, design state machine for the simplifying logic, design the program using the VHDL hardware description language. Besides those,we complete the PCI interface design of simplifying logic and carry out the interface function of the PCI subequipment module on the condition of a 33 MHzs,32 bit width, supporting the transmition paroxysmally. Compared with the traditional PCI inteface which uses appropriative interface chip to carry out this function , it economizes the logic resources of the system, lowers cost, increases the flexibility of design.

其次，在了解PCI规范的前提下，深入地分析了PCI时序和地址配置空间等，设计了简化逻辑的状态机，并用VHDL硬件描述语言设计了程序，完成了简化逻辑的PCI接口设计在FPGA芯片内部的实现，达到了33MHz、32位数据宽度、支持猝发传输的PCI从设备模块的接口功能，与传统的使用PCI专用接口芯片来实现的PCI接口比较来看，更加节约了系统的逻辑资源，降低了成本，增加了设计的灵活性。

At first, this paper gives the brief introduction of the history and present status of accelerometer and its testing technology, the working principium and math model of the liquid floated pendu-lous accelerometer, and then, decides the binary width pulse force retrim loop as the design proposal of testing system, researches the transfer function of every part in the system emphasizly, analyses the stability of the whole accelerometer testing system from the angle of control theoretics by the open loop transfer function of system, and designed the correcting net, analyses the basal problems such as resolution, sampling restraint, precision and so on, designs the hardware testing circuits such as preamplification, band-pass filter, alternating amplifier, phase sensitive demodulatorn, pulse-width modulation, frequency scale circuit, moment current generator. Finally, using the graphics program language LabV-IEW which is designed for testing field especially by NI accomplishes the solfware design of testing system,realized the testing functions.

首先对加速度计及其测试技术的发展历史和现状，液浮摆式加速度计的工作原理和数学模型等作了简要的介绍，然后确定了以二元调宽脉冲再平衡测试回路为设计方案，并从控制理论的角度进行了分析，着重研究了系统中各部分的传递函数，利用系统开环传递函数分析了系统的稳定性，同时设计了系统的校正网络；分析了二元调宽脉冲再平衡测试回路的分辨率、采样约束以及测试精度等基本问题，并按照系统分析的结果设计了包括前置放大、带通滤波、交流放大、相敏解调、脉宽调制、频标电路以及力矩电流发生器等测试系统各部分硬件电路，验证了电路的正确性，最后按照测试系统的要求，采用了美国NI公司专为测试领域所开发的虚拟仪器工具——LabVIEW作为测试软件开发工具，利用该图形化编程语言完成了测试系统软件部分的设计，实现了测试功能。

We design hardware logic for salinometer with Quartus II software, and use SOPC Builder to design Nios II, CPU、arithmetical unit、MEMORY、TIMER and other mature IP core are apply to salinometer. We use the hardware description language VHDL to design bottom drives, and make them as customer IP core, such as excitation source IP core、high sensitive digital galvanometer IP core、analog temperature measurement IP core、digital temperature measurement IP core、calendar and time IP core、keyboard IP core、LCD IP core.

使用SOPC Builder软件生成Nios II软核，将CPU、运算器、存储器、定时器等成熟的IP核应用到盐度计设计中，同时使用硬件描述语言VHDL将底层驱动逻辑设计为用户IP核，如激励源IP核、高灵敏度数字检流计IP核、模拟测温IP核、日历时钟IP核、数字测温IP核、键盘IP核、液晶显示IP核等。

This paper introduces a kind of digital display sphygmometer by using hardware descriptive language VHDL combined with CPLD/FPGA design.

简述了在EDA平台上利用硬件描述语言VHDL结合CPLD/FPGA器件，设计了一种数显式脉搏测试仪。

Theoric analyse and experiment result approved the feasibility and validity of this simple method.

介绍了可编程逻辑器件的发展历程、开发流程、开发环境、硬件描述语言等内容。

Based on the structure and work flow of the system, the thesis describes the design of the communication interface between the uncooled...

本论文按照处理机的工作流程，首先讨论FPGA与视频探测器之间的数据通讯模块的设计，接着介绍了图像预处理模块，在预处理模块中，重点介绍了一种改进的二维中值滤波方法和一种特别适于硬件实现的边缘检测算法；在第四章，讨论了用FPGA实现图像获取和模拟视频输出；第五章，讨论了FPGA与DSP之间以及FPGA与弹上机之间的通讯模块的设计，接着重点研究了一种新的Verilog语言的描述风格，并用此写法在上FPGA实现对外围设备的初始化模块；最后，对本文所做的工作进行了总结。

We have no common name for a mime of Sophron or Xenarchus and a Socratic Conversation; and we should still be without one even if the imitation in the two instances were in trimeters or elegiacs or some other kind of verse--though it is the way with people to tack on 'poet' to the name of a metre, and talk of elegiac-poets and epic-poets, thinking that they call them poets not by reason of the imitative nature of their work, but indiscriminately by reason of the metre they write in.

索夫农 、森那库斯和苏格拉底式的对话采用的模仿没有一个公共的名称；三音步诗、挽歌体或其他类型的诗的模仿也没有——人们把&诗人&这一名词和格律名称结合到一起，称之为挽歌体诗人或者史诗诗人，他们被称为诗人，似乎只是因为遵守格律写作，而非他们作品的模仿本质。

The relationship between communicative competence and grammar teaching should be that of the ends and the means.

交际能力和语法的关系应该是目标与途径的关系。