硬件语言

The content of this course includes: fundamentals of logic algebra analysis and design of the combinational logic circuit and sequence circuit common applications of the combinational logic circuit and sequence circuit programmable logic devices Hardware Design Description Language A/D (Analog/Digital) and D/A conversion.

课程的主要内容有：逻辑代数基础、组合逻辑电路及时序电路分析与设计、常用中规模组合逻辑及时序逻辑电路应用、可编程逻辑器件、硬件设计描述语言VHDL、数模、模数转换等。

A nerve net controller have been designed on the basis of the hardware design of the AC servo system and system model. The controller include two forward nerve net with three layers . One is designed to identify the AC servo system model and another is to control. The controller use special learning algorithm which to control system at the same time and improve its constringency pace through introducing new MFBP algorithm. The intelligent control algorithmic is programmed using C++ language after the controller have been designed .

在该交流伺服系统硬件设计和系统数学建模的基础上，设计了神经网络自适应控制器，这个控制器包括两个三层的前馈神经网络，一个神经网络用于非线性系统的辨识，另一个神经网络作为控制器，此控制器采取边学习边控制的工作方式，并采用一种新型的MFBP算法实现了控制算法的快速性，在控制器设计完成的基础上，利用C++语言具体实现智能控制算法的编写。

Secondly, on the basis of mainboard hardware, the Boot loader table employed in the loading program is introduced as well as the mix program method with assemble language and C language.

二、在系统硬件电路板的基础上，以TMS320C3X汇编语言和C语言为工具，介绍了用于引导装载程序的Boot loader文件表的设计和C语言与汇编语言混合编程的方法。

Hardware circuit is complete, use the C language as a language to control the software shows the whole block.

硬件电路完成之后，使用C语言作为软件语言来控制整个显示块。

and program of DMA transfer data is realized with VHDL language.

提供了基于PCI总线的多通道同步串行数据采集系统的硬件实现方案，分析了整个系统的结构，详细描述了FPGA内部硬件资源的划分和使用VHDL语言实现DMA传输数据的方法和源代码。

VerilogHDL is the most popular hardware description language based on C language.

Verilog HDL 是应用最为广泛的C语言基础上发展起来的一种硬件描述语言。

VHDL is a hardware description language, this book details the specific content of this language.

详细说明： vhdl是硬件系统描述语言，本书详细介绍了此语言的具体内容。

This paper introduced an application of IEEE-488 interface card for PCHardware and software were simple and practical.

本文介绍了一种计算机用IEEE-488接口卡的硬件和软件设计。硬件主要采用一块8255芯片，软件使用C语言。

A new parallel high level data link controller was designed using the hardware description language on the FPGA device. The HDLC protocol controller can construct or deconstruct the multi-channel HDLC protocol frames in parallel way. As a result, it improved the robust and reliability of the whole system.

在FPGA内部采用硬件描述语言并行设计多通道的高级数据链路控制协议控制器，该协议控制器有效利用FPGA的片内硬件资源，实现了并行解析和生成多通道的HDLC协议报文，提高了数据通信系统中的多通道扩展性、实时性和稳定性。

This dissertation lucubrates the architecture of ATS, hierarchical structure and resource models of testing software and the physical structure of hardware.

主要成果是：（1）研究了 ATS 执行机制，首次提出了基于虚拟仪器测试引擎的开放式 ATS 体系结构，从根本上实现了 ATS 硬件无关性和测试代码重用性；（2）研究了采用 IVI、IVI-MSS 和组件技术实现 ATS 仪器互换性的技术与方法，对实现 ATS 网络化奠定了基础；（3）研究开发了测试流程描述语言及相关仪器描述模型、开关矩阵描述模型、测试适配器描述模型，实现了测试软件的结构化和模块化，使大型复杂武器装备测试系统的开发与维护效率大大提高；（4）研究了与 ATS 体系结构相适应的硬件物理结构，该结构实现了 ATS 的通用性、开放性和可扩展性。

We have no common name for a mime of Sophron or Xenarchus and a Socratic Conversation; and we should still be without one even if the imitation in the two instances were in trimeters or elegiacs or some other kind of verse--though it is the way with people to tack on 'poet' to the name of a metre, and talk of elegiac-poets and epic-poets, thinking that they call them poets not by reason of the imitative nature of their work, but indiscriminately by reason of the metre they write in.

索夫农 、森那库斯和苏格拉底式的对话采用的模仿没有一个公共的名称；三音步诗、挽歌体或其他类型的诗的模仿也没有——人们把&诗人&这一名词和格律名称结合到一起，称之为挽歌体诗人或者史诗诗人，他们被称为诗人，似乎只是因为遵守格律写作，而非他们作品的模仿本质。

The relationship between communicative competence and grammar teaching should be that of the ends and the means.

交际能力和语法的关系应该是目标与途径的关系。