电路

Active filter circuit is made of active device and RC network filtering circuit.

有源滤波电路是用有源器件与RC网络组成的滤波电路。

The low pass filter is a seven element circuit based on the circuit and constants described by W3NQN.

低通滤波器是由7个元件组成的电路，它基于由W3NQN所描述的电路与常数。

1 Filter circuit structures modification 48 4.1.1 The first low pass ...

此外，利用设计低电压电路的技巧，在不影响滤波器效能的前提之下，我们成功的将电路的。。。

Next, the finite element model of induction motor is established by using Maxwell 2D transient module, and the inverter control circuit is also designed by its own circuit design editor. Consequently, a complete field-circuit coupled simulation model of inverter control system is presented.

接下来，利用Ansoft公司的Maxwell 2D瞬态模块建立了异步电动机的有限元模型，并且采用其自带的电路编辑器Schematic Capture设计了异步电机逆变器控制电路，构建了一个完整的变频控制系统场路耦合仿真模型。

The read- out integrated circuit is an important interface circuit between infrared focal plane arrays and signal processor.

读出电路是红外成像系统中探测器阵列与信号处理器之间很重要的接口电路。

Therefore, high efficiency can be achieved. The circuit parameters are decided according to the intrinsic impedance of the resonant tank. As the duty ratios of the active switches are fixed, the charging current should be programmed via tuning the circuit operation frequency and therefore the circuit impedance. The optimum operating point is sieved by the frequency response diagram to operate the charger at high efficiency.

至於并联负载电路参数的设计是以共振槽的特性阻抗为基准，调变切换频率并固定主动开关的责任周期，藉由频率的变化改变电路阻抗，以控制充电电流的大小，透过频率响应立体图，挑选适当的操作点，使共振式充电器运作於最佳状态，以获得高效率。

Based on the I-V characteristics of single-electron transistor and the concepts of CMOS digital integrated circuit design, a full adder which consists of 28 complementary SETs is proposed.

基于单电子晶体管的IV特性和CMOS数字电路的设计思想，提出了一种由28个互补型SET构成的全加器电路结构。

Using the proposed method, some neuron MOS circuits realizing two-variable common functions and a full adder are designed, and the ratio of the coupling capacitance in each circuit can be calculated conveniently.

在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路。

Programmable logic gate, I-bit nanopipeline full adder and 4×4 nanopipeline array multiplier based on RTD-CMOS circuits are presented in this paper.

文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟，并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。

The fundamental theorem of CRC and phase-locked loop was discussed.

本文首先从理论上讨论了时钟恢复电路的基本原理与构造，重点放在时钟恢复电路的核心-锁相环的原理和构造上。

For a big chunk of credit-card losses; the number of filings (and thus charge-off rates) would be rising again, whether

年美国个人破产法的一个改动使得破产登记急速下降，而后引起了信用卡大规模的亏损。

Eph. 4:23 And that you be renewed in the spirit of your mind

弗四23 而在你们心思的灵里得以更新