电压线

Within each line, the analog voltage corresponds to the gray scale of the image, with brighter values being in the direction away from the sync pulses.

在每条线里面，类比电压符合图像的灰色刻度，由较明亮的线在水平方向中远离同步脉冲。

The spark-gap phenomenon is the main RF noise source of electrical railways, which happens when the pantograph-catenary is disconnected transitorily.

模型由离线事件模拟器、放电电压条件判决器、触发源等模块组成，将机车车速、定位点跨距、弓网接触压力、受电弓质量、离线概率等诸多因素作为仿真的输入参数，能反映出机车运行时弓网间电火花噪声的动态变化。

On the basis of analyzing the law of variation of the zero order current , the zero order voltage and the zero order power in the isolated neutral system, a synthetic criteria principle of selecting the grounded fault line according to three criterias at the same time was put forward.

在对中性点不接地系统单相接地故障情况下零序电流、零序电压以及零序功率的变化规律做了认真分析的基础上，提出了采用3个判据同时判断的故障选线三合一综合判据原理，这个综合判据可以大大提高接地选线的准确率，具有一定的推广利用价值。

objective to evaluate efficacy of extracorporeal shock wave lithotripsyfor treating ureteral stones in situ,investigate the cause of higher re-treatment rate.methods total of 687 patients with ureteral stone were received eswl between january 2000 and december 2004,included 455 male(66.2%) and 232 female(33.8%) patients,6 cases have bilateral ureteral calculi,12 cases have unilateral multiple calculi.hence,together 709 ureteral calculi were treated.patients upper ureteral calculi were treated in the supine position,for lower ureteral calculi patients were turned prone.to reduce eswl-induced renal trauma and pain,using lower energy source,adjusted power setting from 9.8 to 13.2kv,limited 1500 shock wavs per one session.no auxiliary procedure were used before eswl.the stone size was measured as the surface area of stone length by stone width on x-ray film.the interval between two treatment sessions was two weeks.results of 709 ureteral calculi,the overall stone free rate was 97.3%(690 calculi),re-treatment rate was 34.1%(292 calculi).according to the performed treatment sessions,one session 467 calculi,the mean stone size 37.27mm2,stone free rate 65.4%(464 calculi).two sessions 138 calculi,the mean stone size 62.48mm2,stone free rate 18.4%(131calculi).three sessions 52 calculi,the mean stone size 79.60mm2,stone free rate 7.1%(50calculi).four sessions 19 calculi,the mean stone size 101.63mm2,stone free rate 2.4%(17calculi).fivesessions 33 calculi,the mean stone size 119.33mm2,stone free rate 3.9%(28 calculi).overall 19 cases(2.7%)turned to other treatment modalities.of 335 upper ureteral calculi,303 achieved stone free (95.8%),re-treatment rate was 38.5%(129 calculi).of 374 lower ureteral calculi,369 achieved stone free(98.7%),re-treatment rate was 30.2%(113 calculi).the re-treatment rate of upper ureteral calculi was higher than lower ureteral calculi(p＜0.05,χ2=5.40).the difference of stone-free rate between upper and lower ureteral calculi was no significant(p＞0.05,χ2=0.15).conclusion eswl should be considered first line therapy for ureteral stone still.stone burden are the main variable of higher re-treatment rate,upper ureteral stone may moving with respiring during eswl.so efficinet shock wave was decreared,re-treatment rate become higher.

目的 评估体外震波碎石治疗输尿管结石的疗效，探讨再治疗率高的原因及输尿管结石的治疗选择。方法回顾2000年1月～2004年12月间eswl治疗输尿管结石的临床资料687例，男455例（66.2%），女232例（33.8%），平均年龄46.6岁（15～83岁）。有双侧输尿管结石6例，单侧多发性输尿管结石12例（4颗1例，3颗2例，2颗9例），共计输尿管结石709颗（含透光结石13颗）。应用上海爱申公司生产的desunit6030型碎石机，c臂x线球管做结石定位。上段输尿管结石（肾盂输尿管交界处至骶髂关节上缘）取仰卧位，下段输尿管结石（骶髂关节上缘下至输尿管口）取俯卧位。为减少eswl引起的肾损伤和疼痛，应用较低的能量，震波发生器电压从9.8～13.2kv，震波频率1.5s。每次治疗设定为1500次震波。治疗后3天摄腹部平片或b超，以后每隔7日重复检查。假如结石未碎或有残留结石最长径＞3mm以上，再次eswl，两次治疗的间隔时间为两周。结石的大小用x线片上的表面积（mm2表示。结果 709颗输尿管结石总的治愈率为97.3%（690颗），再治疗率34.1%（242颗）。其中一次治疗467颗，平均结石大小37.27mm2，治愈464颗（65.4%），3颗改治疗；两次治疗138颗，平均结石大小62.48mm2，治愈131颗（18.5%），7颗改治疗；第1和第2次治疗治愈率（1个月治愈率）为83.8%。3次治疗52颗，平均结石大小79.60mm2，治愈50颗（7.1%），2颗改治疗；4次治疗19颗，平均结石大小101.63mm2，治愈17颗（2.4%），2颗改治疗；5次及5次以上治疗33颗，平均结石大小119.33mm2，治愈28颗（3.9%），5颗改治疗。总计19颗（2.7%）结石改变治疗方式。上段输尿管结石335颗，治愈321颗（95.8%），再治疗129颗（38.5%）。下段输尿管结石374颗，治愈369颗（98.7%），再治疗113颗（30.2%）。经χ2检验，上、下段输尿管结石的再治疗率差异有显著性（χ2=5.40，p＜0.05），治愈率差异无显著性（χ2=0.15，p＞0.05）。不良反应：血压升高13例（1.9%），震波区域疼痛26例（3.8%），震波进入处皮肤点状淤血33例（4.8%），肉眼血尿128例（18.6%），均于第2、3天自行消失。结论 eswl目前仍是输尿管结石的第一线治疗，结石的大小是再治疗率高的主要因素。结石的位置有影响，上段输尿管结石可随呼吸移动，有效震波次数减少，再治疗率比下段输尿管结石高。eswl前注重病例筛选可降低再治疗率。

The finished cables shall withstand a test voltage of 1000V, ac, applied between cores and between core and armouring for 5 minutes without breakdown .

成品电缆的线芯间及线芯与铠装之问应经受交流1000V 电压试验5分钟不击穿。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Porous alumina templates with different apertures were fabricated by changing the oxidation voltage in two-step anodic oxidation, and then Cu nanowires were synthesized in porous alumina by the alternating current electrochemical deposition method. The Cu/PAA was analyzed by SEM and XRD, the results have shown that Cu nanowires were indeed synthesized in porous alumina which had the same diameter and good structure of wire grating.

通过改变二次氧化过程中的氧化电压，制备了不同孔径的多孔Al模板；采用交流电沉积的方法，制备了含Cu阳极PAA膜。X射线衍射分析表明，阳极PAA膜上确有Cu生成；扫描电镜显示，Cu纳米线粗细均匀，具有很好的线栅结构。

It is pointed out that the core brittle fracture is caused by extremely uneven voltage distribution along the insulator string and irregular designing and mounting of grading ring which leads to deformation of electric field on conductor end of insulator.It is proposed to replace the suspension clamp by a "八"shape joint strap and installing a glass insulator at this space or introducing a special composite insulator-gla...

通过对原线路双联悬垂复合绝缘子下垂式线夹挂点进行&八&字形改造；利用下垂式线夹缩短的距离在导线侧增挂玻璃绝缘子；新建线路采用特制复合绝缘子与玻璃绝缘子组合方式，使复合绝缘子均压环，接头连接处远离高压端，改善了复合绝缘子的电场分布，降低了复合绝缘子导线端承受的电压，消除了畸变电场，避免了棒形悬式复合绝缘子芯棒脆断，取得了良好的效果。

The existence ofpolar nanoregions dramatically influences the extrinsic dielectric nonlinearityof paraelectric phase. 5 Slow relaxations of field induced piezoelectricresonance of paraelectric barium stannate titanate were observed after eitherapplying or removing a DC bias field. This phenomenon is attributed to slowspace charge dipoles formed by injected homocharges and validated by theobservation of a negative piezoelectric constant. Isothermal study ondielectric constant and discharging current after application or removal of astep field were performed. The relaxation laws in ferroelectric andparaelectric phases are different. The transportation of homocharges arebelieved to be responsible for the strong relaxation behavior in paraelectricphase. Domain wall can trap space charges thus the relaxation in ferroelectricphase is relatively weak. Abnormal phenomena, such as slim-waisted hysteresisloops, abnormal C-V curves and clockwise reversible hysteresis loops observedin barium stannate titanate ceramics, were attributed to pinning of gatheredpoint defect on domain walls.

5研究了直流电场施加和撤除引起的钛锡酸钡顺电相场诱压电谐振慢弛豫现象，认为这是同极性空间电荷注入形成空间电荷慢偶极子导致的，观察到的负压电常数证实了这个观点；研究了等温条件下阶跃电压作用下介电常数和放电电流的慢弛豫现象，发现钛锡酸钡陶瓷的铁电相和顺电相呈现不同的宏观性能时间依赖规律，认为是同极性空间电荷的输运过程导致了顺电相样品呈现强的弛豫行为，铁电相中存在畴壁捕获空间电荷的机制因而其弛豫行为较弱；研究了钛锡酸钡陶瓷中束腰电滞回线、反常 C-V 曲线和顺时针可逆电滞回线等反常现象，将其归因于点缺陷的聚集对铁电畴畴壁的钉扎作用，多次电场循环有助于解除这种钉扎状态，减弱反常特征。

Plunder melds and run with this jewel!

掠夺melds和运行与此宝石！

My dream is to be a crazy growing tree and extend at the edge between the city and the forest.

此刻，也许正是在通往天国的路上，我体验着这白色的晕旋。