流水线结构

This paper brought forward some new design schemes based on the principle and signal processing algorithm of velocity detector, and introduced the hardware construction of the velocity detector based on Depolarizer and S3C2410A microprocessor. The high-efficient ARM program of radical 4-FFT was designed according to the architecture characters of ARM core. In the process of code designing, the instruction scheduling and register allocation were controlled subtly, and the fixed-point number's storage format and computing method of float number were provided. Barrel shifter and 5-lever pipeline were fully utilized and the pipeline interlock was avoided.

针对多普勒测速仪的基本原理和信号处理算法提出了新的设计方案，介绍了由多普勒收发前端和三星S3C2410A处理器构成的测速仪的硬件结构；并结合ARM内核设计特点实现了基4时间抽取快速傅里叶变换算法，针对大多数ARM处理器硬件上不支持浮点运算，提出了把浮点数以定点数格式存储和计算的方法，充分利用桶型移位器和5级流水线，避免了流水线互锁问题。

The high speed advantage of FPGA's operation is made hard to demonstrate for the inconsequence in structural arrangement. The pipeline technology had well solved this problem. We presents a new pipeline optimization technology of inventer's control system based on FPGA,and completed the optimization design of the inventer controller. Analyzed the design process in detail and offered a kind of thought for the people who devoted to FPGA's application in power electronic field.

分析了"流水线操作"等设计优化问题，并针对逆变器控制系统中，控制系统算法呈多层结构，且层与层之间还有数据流联系，其执行顺序和数据流的走向较为复杂，不利于直接采用流水线技术进行设计的特点，提出一种全新的"分层多级流水线"设计技术，有效地解决了复杂控制系统的流水线优化设计问题。

Considering the speed , power dissipation and specifications, A flip-around sample and hold circuit was designed to reduce the power consumption; S/H circuit is followed by eight 1.5-bit stages and a final 2-bit flash sub-ADC.

该流水线式ADC的采样保持电路采用Flip-around结构以减少功耗；前8级每级1.5位，最后一级为2位的并行flash ADC，并采用数字校正技术对级电路的误差进行校正，最终以达到10位的精度；为了达到系统低功耗的要求，该流水线ADC采用了运放共享技术和逐级缩小技术。

Based on soa, this thesis abstracts the dag tasks as pipeline virtual service. taking hsdc telescope data process as the application example, this thesis pays main attention on design and implementation of the pipeline virtual service scheduling algorithm.by analyzing the application characterizations and grid environment, a pvs pre-scheduling model with the relevant sod algorithm and the triangular pyramid scheduling model with tps algorithm are provided in this thesis.

基于面向服务的体系结构，本文将其抽象为流水线虚拟服务(pipeline virtual service，pvs)，并以hsdc系统天文数据处理为例，研究在网格环境下，流水线虚拟服务调度算法的设计和实现。

This thesis analyses the realization difficulty of security modules high-speed handling and large-scale SA entries management. To realize the high-speed handle of data plane, parallel handling and pipeline technologies are introduced to the design of security module, which realizes parallel pipeline high-speed handling structure based on FPGA and high-speed encapsulation/decapsulation of IP data packages on the data plane.

分析了安全模块进行高速处理及大容量表项管理的实现难点，针对数据平面高速处理的要求，将并行处理与流水线技术引入到安全模块的具体设计中，实现了基于FPGA的并行流水线高速处理结构，完成数据平面中对IP数据包的高速封装／解封装处理。

The Pipelined ADC architecture has the characteristics of high sampling rate as well as high resolution.

流水线结构ADC具有能同时实现高采样速率和高分辨率的特点。

9 And 11 based on a multiprocessor controller, and pipelined architectures to speed up the calculations.

2002年8月9日和11 基于多处理机控制器，流水线结构，以加快计算。

Firstly, based on the analysis of basic building blocks, the structure of IDEA is rearranged with eight pipelines.

首先，在分析IDEA算法的基本运算模块的基础上，重新安排了IDEA算法的各个子模块，采用8级流水线结构。

This paper introduced code theory and the common RS codec algorithm, the implementation of RS encoder, then detailedly analyse the decoder realization of BM algorithm and ME algorithm, then bring forward implementation and improvement of a pipeline structure errors and erasures correcting RS decoder on ME algorithm, compromise the decoder complexity and delay to reduce the complexity and raise the maximum operating frequency. Finite-field multipliers optimize codec circuit.

本文首先介绍了编码理论和常用的RS编译码算法，提出RS编码器实现方案，详细分析了译码器的ME算法和改进BM算法的实现，针对ME算法提出了一种流水线结构的纠删纠错RS译码器实现方案，在译码器复杂度和延时上作了折衷，降低了译码器的复杂度并提高了最高工作频率，利用有限域乘法器的特性对编译码电路进行优化。

It is one block of high performance and favorable dynamic-range CMOS Image Sensor.

摘要本文设计了一款10位20MSPS的流水线结构的模数转换器，它是高性能大动态范围CMOS图像传感器的一个子模块。

The labia have now been sutured together almost completely.The drains and the Foley catheter come out at the top.

此刻阴唇已经几乎完全的缝在一起了，排除多余淤血体液的管子和Foley导管从顶端冒出来。

To get the business done, I suggest we split the difference in price.

为了做成这笔生意，我建议我们在价格上大家各让一半。