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时钟脉冲

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According to pulse oddment counting principle,a pulse signal counting circuit for differential ring lasers is designed based on XC3S400AN,a kind of FPGA chip with high performance.

根据脉冲零头计数原理,应用高性能的FPGA芯片XC3S400AN,基于VHDL结构描述语言,对高精度高频率时钟信号进行时序控制及同步处理,设计出一种四频差动激光陀螺脉冲信号计数电路,并进行了实验测试。

According to pulse oddment counting principle, a pulse signal counting circuit for differential ring lasers is designed based on XC3S400AN, a kind of FPGA chip with high performance. The structure of the circuit is described in VHDL language and realized through sequence control and synchronization process of high accuracy/frequency clock signal.

根据脉冲零头计数原理,应用高性能的FPGA芯片XC3S400AN,基于VHDL结构描述语言,对高精度高频率时钟信号进行时序控制及同步处理,设计出一种四频差动激光陀螺脉冲信号计数电路,并进行了实验测试。

The reference clock signal RCLK leads the feedback clock signal FCLK, generating a series of pulses in the DN signal and longer pulses in the UP signal.

在图3中,基准时钟信号RCLK引导反馈时钟信号FCLK,在DN信号中生成系列脉冲,在UP信号中生成较长的脉冲。

By utilizing the cross-gain modulation effect and the period-one oscillation harmonic frequency-locked in an optically injected semiconductor laser, we can extract the wavelength conversional individual channel optical clock from the optical-time-division-multiplexing signal. In a FP-LD, we numerically simulate the extraction of 20 GHz optical clock at 1550 nm from the 2×20 Gb/s OTDM signal at 1555 nm, and experimentally obtain the -105 dBc/Hz phase noise frequency division clock of 12.36 GHz to 6.18 GHz with simultaneous wavelength conversion from 1550.24 nm to 1545.91 nm.

采用一个FP半导体激光器作为全光分路时钟提取及波长转换器,数值模拟实现了从波长为1555 nm、速率为2×20 Gb/s的光时分复用信号中提取出波长转换为1550 nm、重复频率为20 GHz的分路光时钟,实验完成了从波长为1550.24 nm、重复频率为12.36 GHz光脉冲信号中提取出相位噪声为-105 dBc/Hz的波长为1545.91 nm、重复频率6.18 GHz的分频光时钟。

Based on the frequency characteristic of the impulse, electromagnetism interference problem of clock circuit is studied, putting forward basic ways and means for design on the electromagnetic compatibility of clock circuit.

在分析脉冲频谱特性的基础上,研究了时钟电路的电磁干扰问题,提出了时钟电路电磁兼容设计的基本方法。

The power module can supply the power of system. The signal opsonic module will change the voltage signal into the appropriate signals through filter into data processing module. The data processing module analyzes, calculate and deal with the data gathered. The time clock module provides the clock for multi-rate.

电源模块为系统提供电源;输入调理模块将电网中的信号转变成适当幅度的电压信号经过滤波送入数据处理模块;数据处理模块把采集上来的数据进行分析、计算和处理,时钟模块为复费率提供时钟,此外还有脉冲输出模块和通信模块。

The whole PWM circuit contains two subcircuit, the front-end is PWM module that make up of the counter that based on nine MOSFET True-Single-Phase-Clock D flip-flop; the back-end is demodulated module, which is consist of a three order Chebyshev low-pass filter used trans-conductor capacitor. All the subcircuits are simulated. At last, an approving simulated result of the whole circuit is given too.

在调制部分,利用九管单相时钟D触发器构成计数器,并由此组成了脉冲宽度调制电路,同时给出了在典型温度下的仿真结果;在解调部分,介绍了低通滤波器从无源到有源的设计方法,设计了三阶切比雪夫低通跨导电容滤波器,同样给出了相应的仿真结果;最后,作为将脉冲宽度调制电路和滤波器作为整体电路,以脉冲调频波为输入进行了仿真,取得了令人满意的结果。

A design and implementation method of the high speed modulation system, which adopted the new techniques of the FPGA and DAC based communication system,is presented in this paper. The effect of the key techniques of this system, such as the high speed digital signal processing for modulation, high speed based-band signal conversion, wide-band modulation, carrier suppression, high frequency and high precision system clock generation, is analyzed, and the solutions and performance analysis is also given. Finally, a high speed modulation system for space applications is implemented, can be used for high speed data transmission with QPSK, 8PSK, QAM or other kinds of digital modulation.

本论文依据正交调制原理,采用基于FPGA和DAC的设计技术,提出了一种高速、灵活的调制系统的设计方法,重点分析了系统组成的调制编码映射、基带脉冲信号转换、信号滤波、调制、系统时钟产生等关键技术环节的影响,解决了高速调制信号处理、高速数据转换、宽带调制、载波抑制、高频率高精度系统时钟的产生等关键技术问题,完成了一种适用于空间应用的高传输速率、多进制数字调制方式和调制体制灵活的数据传输调制系统的设计与实现,可在硬件设计不变的情况下,实现QPSK、8PSK和16QAM等多种调制方式的高速数据传输,QPSK调制速率达到500Mbps。

Additionally, the author proves the fact that the coordinate differential is embodied in hyperbola intersecting algorithm. 3. Time measurement Based on GPS Time System The basic observation for UGPS is the time that acoustic signal arrives at GIB. To measure the time difference, the time system of every GIB should be synchronized as all GIBs are working independently.

要测量时间差值,必须要求各个浮标系统的时钟严格同步,本文采用了基于GPS时间系统的浮标时钟同步,同时通过GPS接收机的1PPS脉冲校正延时测量漂移,实现精密的时间测量方法。

The clock syncs on the rising edge of the input pulse.

要同步的内部时钟,这个引脚的驱动力必须从0 V至2五对输入脉冲上升沿的时钟同步。

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