时钟周期

Wait state A microprocessor clock cycle in which nothing occurs .

等待状态微处理器不执行任何动作的时钟周期。

This is because the bandwidth required for a lot of time, CPU can only wait until the next clock cycle will be needed, because memory could not keep pace with CPU frequency.

这是由于当对带宽的需求很大的时候，CPU只能够等待下一个时钟周期才能够得到所需要的数据，因为内存的速度跟不上CPU的频率。

It demonstrates that the linear assembly code has a notable increase of the clock cycle efficiency, and the optimization is obvious.

优化后的数据显示，线性汇编代码在时钟周期上效率大幅提高，优化效果相当明显。

Superscalar refers to a clock cycle of a CPU can execute instructions above.

8超标量是指在一个时钟周期内CPU可以执行一条以上的指令。

The resulting system 1 maintains or improves CPU utilization rates as CPU speeds increase, 2 provides large level 1 caches while maintaining cache access times of one CPU clock cycle, and 3 provides high CPU utilization rates for those processing applications where locality of memory references is poor (e.g., networking applications).

随着CPU速度的提高，能够保持或提高CPU的利用率，2）提供大容量一级高速缓存，并同时保持高速缓存的存取时间为一个CPU时钟周期，3）为那些存储器引用局部性不强的处理系统提供高的CPU利用率。

A set of edge-triggered latches which jointly store the state of a binary value through a clock cycle is termed a register.

用一组沿触发锁存器在一个时钟周期内共同地存储一个以二进制数表示的状态，就称为寄存器。

Since the AVR has an 8-bit I/O bus these registers must be written in two execution cycles.

AVR处理器只有一个8位的I/O总线，写入时必须执行两个时钟周期。

The output sequence of i Mealy circuits s one clock cycle earlier than Moore circuits'.

前者比后者的输出序列超前一个时钟周期。

This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle.

这是因为，如果下一个微指令的执行被延迟一个时钟周期，计算机将工作的更快。这个寄存器被称作一个流水线寄存器。

The controller uses the data write buffer to reduce the data access waiting time, and employs the two ways of duo channels instruction pre-fetch buffer to decrease the fetching instruction waiting time and increase the instruction pre-fetch buffer hit rate. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced. Compared with traditional controller through experiments the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss.

该控制器采用数据写缓存方式降低了数据在存取内存时的等待时间；并引入了两组双通道预取指令缓冲器，每组双通道都用以减少取指令时的等待时间，采用两组的结构是为了增加指令预取的命中率；同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率，从而降低了因页失效而需要等待的时钟周期。

In the negative and interrogative forms, of course, this is identical to the non-emphatic forms.

。但是，在否定句或疑问句里，这种带有"do"的方法表达的效果却没有什么强调的意思。

Go down on one's knees;kneel down

屈膝跪下。。。下跪祈祷