时钟周期

An externally controlled address bus selects one of the 108 filters in each clock cycle.

外部控制的地址总线选择在每个时钟周期的108过滤器之一。

At the end of the clock cycle it removes the address from the address bus and deasserts the READ signal.

在这个时钟周期结束时，微处理器撤消地址总线上的地址，并撤消读信号。

All the 32 registers are directly connected to the Arithmetic Logic Unit, allowingcycle.

所有的寄存器都直接与算逻单元相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。

The SAA instruction on a Blackfin processor is fast because it utilizes four 8-bit ALUs in each clock cycle.

一个 Blackfin 处理器的 SAA 指令执行速度很快，因为它在每个时钟周期中可利用4个8bit ALU 。

In the first step, the CPU fetches the instruction byte from memory. To do this, it copies the value of the ip register to the address bus and reads the byte at that address. This will take one clock cycle.

第一步里，CPU从内存取得字节指令，为了做这些，它拷贝IP的值到地址总线并读取在那个地址的字节，这将花费一个时钟周期。

The main goal of CISC designs was to reduce the number of instructions for executing programs.

CISC设计的主要目的是减少用于执行程序的指令数量，而RISC主要是减少每条指令时钟周期的平均数。

This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles.

这发生在一个以上的由低到高的过渡发生在一个时钟周期的多个周期的地方。

Can be started in every clock cycle.

管道线的优点是，尽管完成一个加法花费 5 个周期，但是在每个时钟周期都可以开始一个新的加法。

The major tenet of RISC states that much of the static runtime complexity can and should be handle prior to runtime by an optimizing compiler.

那么最终的硬件结构必须相当简单以确保每条指令单周期的执行以及很短的时钟周期。

After conversion is complete, part of another clock period is required before a high-to-low transition of INTR completes the cycle.

转换完成后，另一部分是在时钟周期的INTR高到低的过渡，需要完成的周期。

In the negative and interrogative forms, of course, this is identical to the non-emphatic forms.

。但是，在否定句或疑问句里，这种带有"do"的方法表达的效果却没有什么强调的意思。

Go down on one's knees;kneel down

屈膝跪下。。。下跪祈祷