时钟

If the output of R1 is 1 then R2 is clocked, R3 is not clocked but its privies repeated.

如果R1的输出为1，那么R2是时钟，R3是时钟不翻转，但其厕所重复。

The MAX3815A features three differential data channels, one clock channel, and an LOS (loss-of-signal) output, which automatically squelches the outputs when a clock signal is not present.

MAX3815A具有3个差分数据通道、一个时钟通道，以及一个LOS输出，没有时钟信号时自动关闭输出。

Also, two independent clocks di- vided down from the high speed clock are available on out- put pins.

此外，两个独立的时钟迪vided从高速时钟下，可从外输入引脚。

LARGE BALANCE WHEEL ELECTRIC CLOCK—This clock is based on the Murday-Reason battery clock manufactured in Brighton at the beginning of the last century.

大平衡轮电动时钟，这是24小时的基础上，穆尔戴-原因电池制造的时钟在布赖顿在上个世纪初。

You must clock in and out using your time card at the beginning and end of your shift.

时钟将设在员工通道口，您需要调整自己的时间表，每次上下班打卡都以时钟的时间为准。

A design and implementation method of the high speed modulation system, which adopted the new techniques of the FPGA and DAC based communication system,is presented in this paper. The effect of the key techniques of this system, such as the high speed digital signal processing for modulation, high speed based-band signal conversion, wide-band modulation, carrier suppression, high frequency and high precision system clock generation, is analyzed, and the solutions and performance analysis is also given. Finally, a high speed modulation system for space applications is implemented, can be used for high speed data transmission with QPSK, 8PSK, QAM or other kinds of digital modulation.

本论文依据正交调制原理，采用基于FPGA和DAC的设计技术，提出了一种高速、灵活的调制系统的设计方法，重点分析了系统组成的调制编码映射、基带脉冲信号转换、信号滤波、调制、系统时钟产生等关键技术环节的影响，解决了高速调制信号处理、高速数据转换、宽带调制、载波抑制、高频率高精度系统时钟的产生等关键技术问题，完成了一种适用于空间应用的高传输速率、多进制数字调制方式和调制体制灵活的数据传输调制系统的设计与实现，可在硬件设计不变的情况下，实现QPSK、8PSK和16QAM等多种调制方式的高速数据传输，QPSK调制速率达到500Mbps。

The number of the frequency division of the method and the circuit structure thereof do not influence the highest frequency of the working circuit. The normal work of the frequency division circuit can be at a comparatively high clock frequency, and the clock frequency division can be realized in the manner of cascade connection of the frequency division circuit so that the scale of the circuit realization can be properly reduced.

本发明所述方法及其电路结构的分频数大小不影响电路工作的最高频率，可以使分频电路正常的工作在相对很高的时钟频率，而且可以通过分频电路级联的方式实现时钟分频，从而可以适当减小电路实现的规模。

The inventive embodiment also discloses a clock card, a cascade MiCroTCA system and a method for providing clocks.

本发明实施例还公开了一种时钟卡、级联的MicroTCA系统和提供时钟的方法。

A new tool that can test the clock base frequency error of energy measuring devices and provide GPS standard time to calibrate real-time clock was introduced in this paper.

介绍了一种用来测量电能计量装置的时钟基频误差，并提供GPS标准时间以校准其实时时钟的新型工具。

The simulation results by HSPICE and Star-sim show that the data can be received correctly under the condition of 1600ppm clock error.

通过HSPICE和Star-sim仿真，对于时钟误差在1600ppm的信号流，该电路可以很好地完成信号的接收并提取正确的时钟。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失