数位电路

Parallel adder is a digital circuit, which can be calculated the number of addition.

详细说明：并行加法器是一种数位电路，其可进行数字的加法计算。

We can use software to do most calculation but not use hardware. The most basic circuit doing calculation in the computer is binary adder. For example, we can use of addition to do subtracting, continuous adding to do multiplication, and continuous subtracting to do division.

在电脑的世界里，可以做任何数字系统且复杂的演算，但是大多数的演算都藉由软体来解决，而非用硬体直接进行各种演算，电脑的硬体或其他数位电路在做算术运算时，最基本的电路往往只有二进位加法器而已，至於减法可藉由补数的加法解决，乘法等於连续的加法，除法则是连续的减法，可见加法器在运算数位系统中的重要性。

The project will develop a bandpass sigma-delta analog-to-digital converter for digital audio broadcasting system in three years. In the first year, we had finished the system simulation for IF receiver using conventional high speed ADC and bandpass sigma-delta ADC, respectively. We also had done the analysis and design of high-order bandpass sigma-delta modulator structure. In this year, we have developed a coefficient synthesis method for high order bandpass sigma-delta modulator using high order filter transfer functions (inverse Chebyshev bandreject filter function).

本计划将在三年内发展一个能应用在数位音讯广播系统的带通sigma-delta类比/数位转换器(analog-to-digital converter，ADC)，在第一年度中我们分别以传统高速类比/数位转换器及带通SD类比/数位转换器的接收系统为例，并结合编码正交多工器(Coded Orthogonal Frequency Division Multiplex，COFDM)的技术，建立一套DAB系统模拟的方法，同时并研究有关高阶带通SD类比/数位调变器的架构及电路，并已成功开发出一个由高阶滤波器合成的高阶带通调变器。

The digital part contains space vector pulse width modulation, simple center computer processor, proportional-integral controller and descend frequency decimator.

整体架构大致可分为数位和类比电路二大部份，数位部份可分为：空间向量脉波宽度调变器、简易中央电脑处理器、比例积分控制器、降频滤波器。

English Description In this course, the VLSI design and fabrication process will be introduced. The students will learn about the characteristics of transistors, digit circuit design methodologies, and system architectures for VLSI. EDA tools will be used in this course to assist in designing the circuit and performing simulations.

Chinese Description 本课程将介绍何谓超大型积体电路及其制程与电晶体基本特性，以及数位电路设计之方法和超大型积体电路系统结构，并使用EDA工具协助电路设计、布局及模拟。

Clock gating is an efficient way of reducing dynamic power consumption in digital circuits.

时钟闸控是降低数位电路动态功率消耗的有效方法。

Therefore, it is significant for analog circuits to operate at the same low supply voltage as digital circuits.

因此，将类比电路操作在与数位电路同样的低电压下更是重要的。

A main ADC architecture for low power system is charge redistribution successive approximation register.In this thesis,8bits sar adc is designed. The main research is sample and hold circuit, D/A convert ,digital control logic etc.

目前在低功率系统中主流的类比数位转换器架构为电荷重新分布式的循渐近式逼近法，本设计8bits逐步逼近式类比数位转换器，主要研究了A/D转换器中包含取样保持电路、D/A转换器、数位逻辑控制等设计。

In high-speed digital system, in order to synchronize the logic gates, use of delay line in board level interconnection is usually required. A popular delay line design is the meander delay line.

在高速数位电路系统中，为使逻辑闸切换能够同步，在做电路板上元件的连接时常须加入延迟线，而最常用的就是蜿蜒型延迟线。

In the last new years , as the demands of wireless communication system grows rapidly , the bands of microwave frequency had been saturated with various communication applications . To achieve wider spectrum for high-speed and high-capacity transmission , bands of millimeter-wave frequency are the solution of this problem . The advantage of MMW wireless communication systems is wider bandwidth comparing with microwave communication systems . To utilize the spectrum efficiently , many methods of complexly digital modulation is proposed . The more complex modulation , the higher linearity is required , and more various phase of signals are required to accomplish process of modulation . Therefore high-linearity and quadrature-phase modulator and demodulator are the emphasis of this thesis . For high level of integration , high performance and low cost , this chip is fabricated by the complementary oxide semi-conductor 0.13um process . A compact size of direct down-conversion and direct up conversion circuits will be presented in this thesis .

近年来随著无线通讯产业的蓬勃发展，微波频带已经趋近於饱和，为了追求更宽的频谱来达到更快传输速率及高资料容量的传输，宽频的毫米波频段提供了解决此问题的途径，毫米波无线通讯系统提供了相对於微波通讯系统宽频的优点，且为了更有效的使用频谱，各种不同且复杂的数位调变方式及方法被发表出来，越复杂的调变方式其所需的线性度越高，且需要更多不同的相位讯号来完成调变的过程，因此高线性度及四相位的调变及解调器将是此篇论文的研究重点，为了达到高整合性，高效能，及低成本的电路设计，我门利用互补式金氧半导体制程来完成此电路设计，因此一小面积的直接降频(Direct down-conversion)及直接升频(direct up-conversion)电路将在文中介绍。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。