接口总线

It has a microcontroller peripheral devices are connected to high-speed bus connections within the connection interface and memory card connection interface, the micro-controller memory card interface, high speed bus interface to connect external devices and virtual within the integrated drive electronics interface module, and the virtual integrated drive electronics interface module includes an integrated drive electronics interface to the virtual host and virtual device side, and when the host side of the card reader connected to the memory card storage or read the instructions issued, the command will be sent to Xuni integrated Shi-driven electronic interface module, and in which the instruction to complete, while the memory card of the information on the transmission to achieve high speed Waiwei components provided within the connecting bus transfer rate, and the host will think that reader is integrated drive electronics interface devices, not just within the high-speed peripheral devices connected bus devices.

其具有微控制器分别连接有高速外围元件内连接总线连接接口及存储卡连接接口，而微控制器具有存储卡接口、高速外围元件内连接总线接口及虚拟整合式驱动电子接口模块，且虚拟整合式驱动电子接口模块包括有整合式驱动电子接口的虚拟主控端及虚拟装置端，而当主机端对读卡机所连接的存储卡下达储存或读取的指令时，该指令会传送至虚拟整合式驱动电子接口模块，并在其中将指令完成，而存储卡内的资料于传输时可达到高速外围元件内连接总线所提供的传输速率，且主控端会认为读卡机为整合式驱动电子接口装置，而非单纯的高速外围元件内连接总线装置。

This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kind of bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of corresponding software and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design.

介绍将CAN总线接口与RS232总线接口相互转换的设计方法和2种总线电平转换关系，实现CAN总线与各模块的接口设计，制定了相应的软硬件设计方案，并给出软件设计流程图以及部分硬件设计原理图。

PCI bus is a high performance architecture for high - speed peripheral device.

PCI总线是一种高性能的高速外围设备接口总线。

The current integrated well log instrument with multiple bus data transfer is improved by using pulse-code modulation and time division multiplex.

利用脉码调制技术和时分复用技术对现有的多总线数据传输综合录井仪进行改进，通过在井台区设置一个接口箱，使录井仪的主机柜与接口箱之间只用一根总线连接，变多总线数据传输方式为单总线数据传输方式。

Design of CSD Code FIR Digital Filter Based on Time Division Multiplex;2. The current integrated well log instrument with multiple bus data transfer is improved by using pulse-code modulation and time division multiplex .

利用脉码调制技术和时分复用技术对现有的多总线数据传输综合录井仪进行改进，通过在井台区设置一个接口箱，使录井仪的主机柜与接口箱之间只用一根总线连接，变多总线数据传输方式为单总线数据传输方式。

All these problems still need to be solved. So, towards the IP Core interface compatibility of SoC Bus standard, this thesis, based on analyzing the interconnection of IP Cores, researches the software capsulation of IP Core Bus interface layer, and implements the IP Core interface layer of embedded system developing platform which is based on layers. In this thesis; the design method, flow, and environment of SoC based on IP demultiplexing is explained. While in order to improve the integration of IP Core on SoC, interconnection rules of IP Core and its standardization are researched.

鉴于此，本文在对IP核互连进行分析的基础上，针对SoC总线标准的IP核接口的兼容问题，研究和设计了IP核总线接口层的软件封装，并将其作为课题组提出的基于层次的嵌入式系统开发平台的IP核接口层予以实现，使上层开发人员可以根据此规范快速开发出基于该开发平台的IP核，也使得遵循该接口规范的IP核在无需了解具体SoC互连信息的前提下即可实现核内传输机制，从而提高了SoC设计的可复用性。

Control and management system of facilities for smart home ;2. In allusion to lacking of a universal standard criterion and interface protocol on domestic smart home network , CEBus, home bus protocol, the design for home gateway and bus interface criterion are mainly discussed.

针对国内智能家庭网络缺乏统一的标准规范和接口协议，重点论述了消费总线、家庭总线协议，以及家庭网关的设计和总线接口标准，提出了家庭网络由高速信息子网和低速控制子网组成，控制子网提供的服务和应用在智能住宅中最具实用价值，也是智能住宅设计中的难点所在。

The invention provides a dual redundant CAN bus controller, which is arranged on a crewel CAN bus, characterized in that: two CAN bus transceiving modules, two initializing modules are respectively corresponding to the CAN bus controller module A and CAN bus controller module B; the two CAN bus controller modules are respectively connected to the two CAN bus via a driver shifting control unit; the initializing module is connected to the bus control initializing register for initializing the e CAN bus controller modules; a protocol processing module is connected to the FIFO buffer; the FIFO buffer is connected to the node processor via the logical interface; a intermitting process unit sends the corresponding intermitting control signal to the CAN bus transceiving modules according to the CAN bus controller modules; one path of the CAN bus controller module is directly connected to the protocol processing module; another path is connected to the protocol processing module via the bus receiving buffer.

本发明提供了一种双冗余CAN总线控制器，设置于双线CAN总线上，其特征在于：两个CAN总线收发模块、两个初始化模块分别与CAN总线控制器模块A和CAN总线控制器模块B相对应；两个CAN总线控制器模块通过驱动器切换控制单元分别与两条CAN总线相连；初始化模块与总线控制器初始化寄存器相连，对所对应的CAN总线控制器模块进行初始化；协议处理模块与FIFO缓存器相连；FIFO缓存器通过逻辑接口与节点处理器连接；中断处理单元根据CAN总线控制器模块的控制命令对CAN总线收发模块发出相应的中断控制信号；CAN总线收发模块一路与协议处理模块直接相连，另一路通过总线接收缓存器与协议处理模块相连。

The first of the I2C-bus design of the Avalon bus interface specifications and a preliminary understanding, the use of Verilog HDL language of I2C modules were prepared, and then carried out Modelsim compiled simulation software simulation, simulation waveforms obtained, and finally to adopted by the compiler to achieve the I2C IP core in the SOPC BUILDER module can generate nuclear IP core, the IP core of the I2C is Avalon bus interface, and then prepared NiosII system testing software, to achieve the functions of I2C bus.

本设计先对I2C总线的规范和Avalon总线接口进行了初步的了解，使用Verilog HDL语言对I2C的各个模块进行了编写，然后在Moelsim仿真软件内进行编译仿真，得出仿真波形，最后把编译通过的，实现I2C总线IP核的模块在SOPC BUILDER中生成可以调用的IP核，这个I2C的IP核是采用Avalon总线接口的，然后在NiosII中编写系统测试软件，实现I2C总线的功能。

At first, this paper introduces the receiving and transmitting mechanism about the ARINC629 data based on the ARINC629 protocol. With the computer interface technology, it gives the whole design of the communication card which is divied into three modules, such as the PCI bus interface module, the subsytem processer and memory module and the ARINC629 bus interface module.

论文首先根据ARINC629总线协议规范，明确了ARINC629总线协议的数据发送和接收机制，并结合当今计算机接口技术，确定了数据通信卡的总体方案，将数据通信卡划分为三个模块进行设计，即PCI总线接口模块，通信卡子系统处理器和存储器模块以及通信卡与ARINC629总线接口模块。

The labia have now been sutured together almost completely.The drains and the Foley catheter come out at the top.

此刻阴唇已经几乎完全的缝在一起了，排除多余淤血体液的管子和Foley导管从顶端冒出来。

To get the business done, I suggest we split the difference in price.

为了做成这笔生意，我建议我们在价格上大家各让一半。