指令的

AT FIRST THIS PAPER DESCRIBES THE PIPELINE STRUCTURE, INSTRUCTION SET, INSTRUCTION CODE, AND PIPELINE HAZARD.

阐述了MIPS五级整数流水线结构相应的指令功能及编码，以及流水线竞争中结构竞争数据相关等问题。

Data is written in 16 bits per write instruction into the selected register.

数据是写在每16位寄存器写入选定的指令。

To improve data transmission rate of JTAG interface, instruction register and related control logic are redesigned.

为了提高JTAG接口的数据传输效率，指令寄存器和相关控制逻辑被重新设计。

Like the Load and Add , there are variations of this instruction depending on the register specifier and the addressing mode .

就像载入和加法，这指令有许多的变动取决於暂存器指标和定位模式。

Simple addressing modes,with all load/store addresses being determined from register contents and instruction fields only.

简单寻址模式，所有的加载/储存地址仅由寄存器内容和指令域决定。

The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued.

接下来的2位（R1和R0）选择4个寄存器，是一个必须采取行动时发出指令寄存器导向。

LSPn. This control block receives input from the STA111 instruction register, mode registers, and the TAP controller.

。这个控制块接收来自STA111指令寄存器的输入，模式寄存器和TAP控制器。

Instructions can be prefixed with the name of one of the predicate registers, and the CPU will only execute the instruction if the register equals True.

即只有相应的断言寄存器中值为"真"时CPU才会执行指令，不然CPU就执行一条

The execution environment described here includes memory, general purpose data registers, segment registers, the flag register, and the instruction pointer register.

此处描述的执行环境包括内存、通用目的数据寄存器、段寄存器、标志寄存器和指令指针寄存器。

Book on the ARM architecture, instruction system and development tools were introduced.

本书对ARM的体系结构，指令系统和开发工具作了全面介绍。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。