指令地址

In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address of PC-relative and absolute address branch instructions.

在流水线式处理器中，位于指令高速缓存之前的预解码器计算PC-相对和绝对地址转移指令的转移目标地址。

In particular, the branch instruction is evaluated as ''mispredicted not taken'' with a branch target address of the incorrectly pre-decoded instruction's address.

明确地说，所述分支指令被评估为"错误预测为不采取的"，其中以所述未经正确预解码的指令的地址为分支目标地址。

The pre-decoder compares the BTA with the branch instruction address to determine whether the target and instruction are in the same memory page.

所述预解码器将BTA与转移指令地址进行比较，以确定目标与指令是否位于相同的存储器页内。

Thus, whenever a branch instruction is encountered the disassembly continues simultaneously at both the address following the branch instruction and the address that is the target of the branch instruction.

因此，无论何时遇到一个分支指令，就同时从两个地址继续反汇编：分支指令后面的地址和分支指令的目标地址。

This is silly, because I should still be able to set a breakpoint based on the instruction address.

这是愚蠢的，因为我仍然可以设置的指令地址的一个断点。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

A need to access the instruction address stream.

产生一个需要访问的指令地址流。

Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units.

能针对一个或多个特定的存储单元调整将该指令地址译码为一个物理地址的过程。

Instruction pointer A register in the processor that contains the address of the next instruction to be executed.

包含下一条要执行指令地址的处理器中的寄存器。

Instructions are fetched from consecutive memory addresses, starting from address zero, until an instruction which modifies the PC is executed, whereupon fetching starts from the new address given in the 'jump' instruction.

指令从存储器的0地址开始顺序读取，直到执行到修改PC的指令为止。到那时则开始从jump指令给出的地址读取指令。

This one mode pays close attention to network credence foundation of the businessman very much.

这一模式非常关注商人的网络信用基础。

Cell morphology of bacterial ghost of Pasteurella multocida was observed by scanning electron microscopy and inactivation ratio was estimated by CFU analysi.

扫描电镜观察多杀性巴氏杆菌细菌幽灵和菌落形成单位评价遗传灭活率。