延迟电路

Detail programmable logic design circuity is presented. The circuitry of each chute is separated and similar, which includes impute module, storage module, delay module, serial communication module comparing module and output module, etc.

给出可编程逻辑器件的具体电路设计，PLD的每路信号处理电路独立且相同，共划分输入模块、存储模块、延迟模块、串行通讯模块、比较模块、输出模块等6个模块。

The oscillator has no connection with any oher component and it just brings about vibartion through the delay of circuit.

与非门构成的可控环形振荡器由于没有外接任何元件，它依靠门电路自身的延迟时间而形成振荡，因此，其振荡频率很高，为提高抢答组之间的分辨时间提供了条件。

The transmission apparatus for half duplex communication using HDLC includes: a clock generator, an HDLC controller, flag delay/detecter device, a control logic circuit and an output controller.

其包括时钟发生器、HDLC控制器、标记延迟／检测装置、CPU、控制逻辑电路和输出控制器。

As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area.

例如，在4位行波进位加法器中，第2级和第4级的加法器不需要用输出反向器进行进位产生，因此，加法器链上的反向器延迟每两级全加器抵消一次，因此可以减少4个晶体管，类似的，在乘法器这样的复杂设计中，用于产生"和"以及"进位"的输出反向器可以用于其它方面，因此可以改善电路的速度和减小面积。

Trigger control circuit in accordance with pulse phase and input along the angle of the trigger value, the corresponding time delay after the rising edge of trigger pulse, open SCR, and in the corresponding half-cycle before the end of hair falling edge trigger pulse, turn-off thyristor, for the next half cycle of the trigger ready.

触发控制电路根据鉴相脉冲沿和输入的触发角数值，延迟相应时间后发出触发脉冲上升沿，打开可控硅，并在相应半个周期结束前发触发脉冲下降沿，关断可控硅，为下个半周期触发做好准备。

The method of "Logical Effort Delay Model" allows designers to quickly estimate delay time and optimize logic paths, but the previous variances of logical effort models do not mention how to handle process, voltage, and temperature variations appropriately, which may induce a serious misestimate.

Logical Effort Delay Model是一个可让电路设计者以简便的手算方式快速估计电路延迟并完成初步电路最佳化的方法。

Introduced the principle of this angel measuring system first. Then discussed the interface circuit between the AD2S82A and the DSP controller in detail.At last,gave a multi channel and high speed interface circuit which is composed of 3-state latches and monostable multivibratores.

介绍了这种测角系统的组成和工作原理，研究了它与DSP处理器的接口问题，并利用三态锁存器和单脉冲触发芯片，设计出了一种适用于多通道系统的高速接口电路，解决了DSP一次读取多片AD2S82A所造成的大量时间延迟问题。

In high-speed digital system, in order to synchronize the logic gates, use of delay line in board level interconnection is usually required. A popular delay line design is the meander delay line.

在高速数位电路系统中，为使逻辑闸切换能够同步，在做电路板上元件的连接时常须加入延迟线，而最常用的就是蜿蜒型延迟线。

Frequency Synthesizer; Phase Locked Loop; Voltage Controlled Oscillator; Multiple-pass Delay Cell; Dynamic voltage-mode; Phase Interpolation; Quality Factor; Process and Temperature variation; Self-adaptive; Phase Noise; Jitter; Analog circuit

信息科技，无线电电子学，基本电子电路频率综合器；锁相环；压控振荡器；环形振荡器；多通路环延迟单元；动态电压模；相位内插；品质因子；工艺温度波动；自适应；相位噪声；抖动；模拟电路

Compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high-speed circuit design. Anda retiming scheme based on the above method is also presented to optimize the timing behavior of sequential circuits.

同传统方法相比，本方法计算出的最小周期既能保证电路的正确计算，又不至于保守，而且能同时计算出组合逻辑部分的延迟；然后从时序电路的波形多项式出发，进一步给出了多周期敏化的最小时钟周期确定方法，适用于有苛刻定时要求的环境。

On the other hand, the more important thing is because the urban housing is a kind of heterogeneity products.

另一方面，更重要的是由于城市住房是一种异质性产品。

Climate histogram is the fall that collects place measure calm value, cent serves as cross axle for a few equal interval, the area that the frequency that the value appears according to place is accumulated and becomes will be determined inside each interval, discharge the graph that rise with post, also be called histogram.

气候直方图是将所收集的降水量测定值，分为几个相等的区间作为横轴，并将各区间内所测定值依所出现的次数累积而成的面积，用柱子排起来的图形，也叫做柱状图。