延迟电路

In the analysis of combinational logic circuit, should take into account gate delay time of the impact on the circuit.

在分析组合数字逻辑电路时，应该考虑门电路的延迟时间对电路产生的影响。

The single edge-triggered flip-flop uses low swing voltage delay chain, conditional capture technique and stacked technique to reduce the power consumption.

此单缘触发正反器使用了低震荡电压的时间延迟电路、条件性撷取技术和电晶体叠加技术来达到低功率设计。

The single edge-triggered flip-flop uses low swing voltage delay chain generating the operation transparency window for reduces the power consumption.

此单缘触发正反器使用了低电压的时脉震荡延迟电路，来产生操作的触发波形和电晶体叠加技术，来达到减低漏电流的低功耗设计。

On the design of algorithms, a novel exact hierarchical delay analysis method for general circuits is proposed; based on the sensitization theorem for sequential circuits, an exact minimizing clocking method is proposed; based on Boolean process, a waveform simulation method considering interconnecting delay for logic circuit and a parallel waveform simulation method are proposed; a new method that transforms bit-level waveform polynomial to word-level polynomial model is proposed; a multiple valued synthesis algorithm based on multiple valued Boolean process and a wire-centered delay synthesis policy are proposed, in which timing planning, floorplanning, wire planning and optimal clock skew in early design are considered; a two-layers channel routing method for minimizing crosstalk under grid mode is proposed; based on the transition numbers theorems for waveform polynomial, a new method for generation of test with noise effects is proposed.

算法设计方面，提出了一种精确的通用电路层次化延时分析方法；基于时序电路的敏化定理提出时序电路最小时钟周期精确确定方法；提出基于Boolean过程论的考虑互连延迟的逻辑电路波形模拟方法，在分析了波形模拟适合并行化基础上，进一步提出一种并行波形模拟算法；提出一种将位级电路波形多项式描述转化成字级多项式描述的新方法；提出一种基于多值Boolean过程的多值电路综合算法以及一种将前期设计定时规划、前期设计的布局规划和线网结构化方法及低偏移的时钟分配等技术相结合的面向互连延时的综合策略；提出一种串绕最小化的网格模式下的双层通道布线方法；从波形多项式描述跳变数的定理出发提出了一种考虑噪声效应的测试生成新方法。

It consists of many ele- mentary pulse networks such as: Transistor forming and shaping circuit,trrnsistor blocking oscillator,multivibrator,time delay circuit and "and" gate,etc.

本文专门讨论了利用脉冲选择的晶体管化同步分频系统的线路综合原理和研制技术问题，对组成系统的各种单元脉冲电路，如晶体管窄脉冲形成器，晶体管间歇振荡器，晶体管多谐振荡器，晶体管延迟电路以及晶体管门电路等均作了较深入的分析，并给出相应的实验结果。

By rational configuration of the low voltage solid circuits and hydrogen thyratron circuits,long precise delay and low jitter of high voltage output can be obtained.

采取低压固体电路与大小氢闸管电路的合理配置，较好地解决了精密长延迟和高压脉冲输出时低延迟时间晃动的难点。

We designed the multi-channel delay and pulse adjustment circuit based on CPLD providing a solution to fast gating timing and delay problems in large nuclear physic experiments. Its main function is accepting a negative NIM trigger input, and outputting a pulse with adjustable delay and width. Minimum step accuracy of the delay and the pulse adjustment is 10ns when the system frequency is 100MHz.

针对大型核物理实验中的符合测量、多路时间测量系统中的门控快定时信号等应用的需要，设计了一种多路延迟／脉宽调节电路，主要功能是对输入的多路快信号进行延迟和脉宽调节，支持NIM负信号输入和输出，在系统主时钟频率为100MHz的时候，延迟和脉宽调节的最小步进精度为10ns。

Under power supply voltages 5, 3.3, 1.8 V, using 0.24 μm process to carry out PSPICE simulation, the proposed XOR gate can save power consumption up to 36.5%, while power-delay-product up to 68.0% as compared with the published designs, which shows that the proposed design has advantages in power and delay.

在5、3.3、1.8 V电源下，经PSPICE在0.24μm工艺下模拟，与已发表的异或门电路设计相比，新提出的电路功耗和功耗延迟积的改进分别高达36.5%和68.0%，说明本文设计的异或门电路在功耗和延迟方面具有优势。

The present paper uses 555 time base circuits and the photoresistance to make a delay circuit, and it can solve the above problem efficiently.

本论文就是使用555时基电路和光敏电阻来做一个延迟电路，它能有效的解决上述的问题。

The proposed designs are realized using TSMC 0.18 um 1P6M CMOS process. The voltage supply is 1.8 V. The simulation tool used is HSPICE. According to our comparison, the proposed designs possess the advantages of lower power consumption and lower power-delay product.

电路是使用TSMC 0.18μm 1P6M制程来实作，电路的供应电压为1.8V，并用HSPICE 来进行模拟与分析，而实验结果证明本文所提出的新的低功率Compressor电路，跟相同性质的电路架构相比较后，有较低的功率消耗，以及较低的功率与延迟的乘积。

So that more consumers can enjoy more delicious quality, technology is even better than wine.

让更多的消费者可以品尝到品质更为鲜美，工艺更为精湛的葡萄酒。

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在你最喜爱的文本编辑器中将它打开。