并行操作

A group of tracks on a magnetic drum or on a magnetic disk all of which are read or written in parallel.

磁鼓或磁盘表面上的一组磁道，可以并行地对它们进行读／写操作。

The FunkyMD Suite aims to provide tools for titling, editing, recording and remote controlling MiniDiscs using a portable MiniDisc recorder such as the Sony MZR-900 and a self- made interface for the parallel port.

FunkyMD Suite目标是提供标题烫印、编辑、记录和遥控操作唱片的工具，使用一个便携式的唱片记录机，如：索尼的MZR-900和一个自做的并行端口界面。

For improving the parallelizability of the co-processor, a set of new efficient instruction is introduced, including S-boxes substitution, general bit permutations, arbitrary rotates, modular arithmetic and so on.

从提高并行度角度出发，为使用频率非常高的密码操作，包括S盒、置换、模乘、模加等九种运算设计了专用指令。

Log file initialization still requires zeroing, but it will happen in parallel with the transfer of the data from the backup.

日志文件初始化仍需要零位调整，但此操作将与从备份传输数据并行进行。

The data layout of parallel storage system was completed by using rebalancing operations of simulation data repetitiously so as to make the nodes extension of the system more easily.

它通过多次模拟数据重均衡操作来完成并行存储系统的数据分布，从而使得系统更易于节点扩展。

This article argues that full-parallel algorithms of traditional sigmoidal neural networks based on average fire rate which have excluded useful time operation seem improper for the invariance.

郭雷(西北工业大学自动控制系，西安 710072)本文表明传统的基于脉冲平均点火率的人工神经网的全并行计算是不妥的，因为它不能进行时间操作。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Using the quantum parallel process and quantum permutation orations, the circuit implementation of quantum binary searching algorithm is presented.

利用量子并行处理和量子置换操作，给出了量子二分检索算法的线路实现。

Busparallel expansion and pipeline technique are adopted to improve the average inputand output speed of recorder based on FLASH memory. 2 A concept of 'cluster' isintroduced. The using state message of each cluster is loaded in the spare area,following the target datum, to keep the pipeline sequence of multiple clusters' loading, which guarantee the average input speed of system. 3 Based on the using statemessage of every cluster, the Cluster Allocation Table established in memory enablethe system to manage the recorder flexibly in high speed, similar to a file managementsystem. 4 PowerPC 8245 based embedded system, along with Vxworks real-timeoperating system is introduced to make the system more easier to be applied to theprojects in the future.

本文所述的关键技术特点主要包括：采用了并行扩展以及流水线操作技术以提高基于FLASH芯片的存储区平均输入输出能力；引入了&簇&的概念，为了保证连续写入过程中的流水线顺序，系统向存储区加载每一簇有效数据后，紧接着还将向相应簇的空余区中加载该簇的使用状态信息；根据所有簇的使用状态信息在系统内存中建立&簇分配表&，可以支持系统快速灵活地管理存储区，即，类文件化的数据管理；采用基于PowerPC8245的嵌入式计算机硬件系统及基于Vxworks的嵌入式实时操作系统，提高了系统的整体性能及系统研发的延续性。

I am accused of being overreligious," she said in her quiet, frank manner,"but that does not prevent me thinking the children very cruel who obstinately commit such suicide.""

客人们在卡罗利娜·埃凯家里，举止就文雅一些，因为卡罗利娜的母亲治家很严厉。

Designed by French fashion house Herm è s, this elegant uniform was manufactured in our home, Hong Kong, and was the first without a hat.

由著名品牌 Herm è s 设计，这件高贵的制服是香港本土制造，是我们第一套不配帽子的制服。