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The measured object can be found within a few milliseconds in the raster-scan image. 4 . Two lines delay for the processed image is implemented using two 128×8 shift registers with the configurable logic block in FPGA. A new fully pipelined bit parallel hardware architecture for Sobel edge detection is implemented with FPGA. Furthermore, it takes no more than 2ms to complete the edge detection of an image with 128×128 pixels.

视觉检测信号的前端处理技术 1、系统地分析了视觉检测算法层次性特点和计算特点,提出了提高视觉检测信号处理速度的基本方案:采用前端处理系统,自动识别被测物体在获取图像中的位置,并将真正有用的被测物体的边缘坐标值,提供给计算机,作进一步的高精度处理; 2、系统研究了实时图像硬件处理的设计基本方法,提出了基于FPGA的视觉检测信号的低级处理算法硬件实现模块化模型; 3、提出了一种新的基于FPGA的模板匹配并行模块化结构,解决了二维图像处理高带宽要求,在几毫秒内就可以在按扫描顺序输入图像中找到检测目标物体的位置; 4、采用FPGA内部的可配置逻辑块实现了128×8移位寄存器的设计,解决了大容量移位寄存器与FPGA内部寄存器数量之间的矛盾,实现了两行图像的延迟。

This design primary mission is completes the static heavy accelerator the principle and the design proposal, its main design mentality is: Determines in the vessel by the sensor the fat liquor quality, carries on the cyclical sampling under the certain time-gap, transforms after the A/D switch, bequeaths the initial datum the register, the afterwards data bequeaths CPU, the register cancels with some time data namely for flows out the fat liquor the quality, again demonstrates its value by the monitor

本设计的主要任务是完成静重式加油机的原理及设计方案,其主要设计思路为:由传感器测出容器内油液质量,在一定的时间间隔下进行周期采样,经A/D转换器转换,将初始数据传给寄存器,随后的数据传给CPU,寄存器与某时刻的数据相减即为流出油液的质量,再由显示器显示其数值。

Register allocation is an important optimization of compiler back end. Register allo-cator determines which of the values, including variable, temporaries ,and large constants, that might profitably be in a machine's registers should be in registers at each pointin the execution of a program.

寄存器分配是编译后端优化中的重要技术,寄存器分配需要决定在程序执行时,哪些值(包括变量,临时量和大的常量)放在寄存器中会更有利。

This is a dynamic method, according to all the pressure of each clusters register, which can reduce register spill and improve the efficiency of the program.

通过考察指令运行时的寄存器压力情况对指令进行分簇,这样可根据各个簇的寄存器压力的动态信息减少寄存器的溢出,提高指令运行效率。

Register is one of the most valuable resources. Software pipelining could bring about register pressure while scheduling instruction of VLIW DSP, which would cause register spill and software pipelining suspension.

寄存器是程序运行时最宝贵的资源之一,软件流水在对VLIW DSP指令调度的同时,会显著增加寄存器的压力,从而导致寄存器溢出,软件流水中止。

This paper evaluates the register requirements of software-pipelined loops and presents three new methods for software pipelining loops that require more static general registers than those available in Itanium processor. They reduce register pressure by either reducing instructions in the loop body or allocating stacked non-rotating registers or rotating register in register stack to serve as static registers.

在Itanium处理机上评估了NAS和SPEC2000基准程序中的软件流水循环的寄存器需求,发现静态寄存器不足是造成软件流水失败的主要原因,提出了3种增加软件流水个数、提高软件流水有效性的算法:限制循环展开因子的算法(register sensitive unrolling,简称RSU)、堆栈寄存器分配算法(stacked registerallocation,简称SRA)以及变量类型转换的算法(variabletype conversion,简称VTC)。

The data location includes memory data memorizer and memory map register, which share uniform data and address buses, at the same time occupy independent physical spaces, respectively, both physical and logic addresses separated and independently addressed, respectively, and can multiplex the same logic address.

内存数据存储器和内存映射寄存器共享统一的数据总线和数据地址总线。同时,内存数据存储器和内存映射寄存器各自占有独立的物理空间,物理地址和逻辑地址均分开,各自独立编址,内存数据存储器和内存映射寄存器对同一逻辑地址可以复用。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外更有Index寄存器:他有6位能够由软件配置,和Random寄存器:一个6位的每个时钟周期都很递减的寄存器,并且不会小于8。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外还有Index寄存器:它有6位可以由软件设置,和Random寄存器:一个6位的每个时钟周期都很递减的寄存器,并且不会小于8。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外更有Index寄存器:他有6位能由软件设置,和Random寄存器:一个6位的每个时钟周期都非常递减的寄存器,并且不会小于8。

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