寄存

Now HLS has absorbed much research attention in IC-CAD field. In HLS, algorithms represented by algorithm description language are transformed into hardware structure description consisted of resisters and transfers. In the transforming process, synthesis of datapath is a core. The other works is based on it. And in the synthesis of datapath, operation scheduling, functional unit allocation and binding all are NP-Completeness problems. The structure of their solution space is not known well. If we must find a global optimum solution, we can only use exhaustion. This way needs too much computation for VLSI synthesis, and is impractical in Industry. So usually heuristic algorithms are used to search suboptimum solution.

因此HLS成为国际IC-CAD学界的一个热门，它把算法描述语言表达的算法转换为用寄存器、传输器描述的硬件结构，其中以数据通路的综合为主体，其余工作皆以此为基础；而在数据通路综合中，操作调度、功能单元分配、连线等均属NP问题，目前该问题的解空间尚未充分了解，如要求得最优解，只有采取穷举搜索法，对于大规模集成电路而言运算量太大，工业中无法承受，故通常都采用启发算法求次优解。

In the digital control module of the circuit, design the successive approximation logic which based on the ring counter/shift register.

在数字控制模块的电路实现中，用基于环形计数器和移位寄存器的结构设计了逐次逼近逻辑电路。

The coarse tuning structure is composed of two digital modules, including a successive approximation register and a frequency comparator with a novel structure.

该粗调环路由数字电路设计实现，包含逐次逼近寄存器和新结构的频率比较单元两个模块。

This paper proposed a Superblock based dynamic data prefetching scheme for dynamic translation, it used software instrumentation to collect program's load delay information and built Superblocks. Then performed the data flow analysis on Superblocks to generate the RDUG. After that, inserted data prefetching instructions for the delinquent loads.

基于超级块的动态数据预取优化采用软件插桩方式收集应用程序的load访存延迟信息并构造Superblock；然后根据延迟信息以及Superblock数据流分析得出的寄存器定值引用关系，对延迟load指令进行预取优化。

This paper proposes a SuperBlock based dynamic data prefetching scheme for dynamic translation, it uses software instrumentation to collect program's load delay information and build SuperBlocks. Then the data flow analysis is performed on SuperBlocks to generate the RDUG. After that, data prefetching instructions are inserted for the delinquent loads.

基于超级块的动态数据预取优化采用软件插桩方式收集应用程序的Load访存延迟信息并构造SuperBlock，然后根据延迟信息以及SuperBlock数据流分析得出的寄存器定值引用关系，对延迟Load指令进行预取优化。

This can be achieved by using pre-indexed addressing with auto-indexing, and allows the program to walk through a table of values

可以使用带有自动变址的前变址寻址来实现对基址寄存器的修改，这样可么让程序追踪一个数据表，即

When no hardware tessellation is used, the shader is unaware of what data are

硬件镶嵌的时候，着色器根本就不知道输入寄存器中载入的是什么数据。

As a matter of fact , when no hardware tessellation is used , the shader is unaware of what data are loaded in the input registers .

事实上，不使用硬件镶嵌的时候，着色器根本就不知道输入寄存器中载入的是什么数据。

Data can be supplied either by the vertex buffer or by the primitive tessellation engine.

一开始，输入寄存器的编号和其功能之间没有严格的对应关系，比如某个顶点的坐标既可以被载入v0，也可以被载入v15。

Taking the high precision on chip RTC as the time base control unit and using genetic algorithms to search the best OSCCAL register value, it will make the on chip RC oscillator generate a high precision clock for the MCU. This methord can be used fast and real time, so the CPU will get a stable clock source.

以AVR片内高精度时钟单元RTC为时基控制单元，以标准时间内MCU定时器的计数值为控制目标，采用遗传控制策略搜索对应MCU理想时钟频率的OSCCAL寄存器最佳设置值，快速、准确地对RC振荡频率进行校准，为CPU提供具有高抗干扰特性的精确时钟。

With Death guitarist Schuldiner adopting vocal duties, the band made a major impact on the scene.

随着死亡的吉他手Schuldiner接受主唱的职务，乐队在现实中树立了重要的影响。

But he could still end up breakfasting on Swiss-government issue muesli because all six are accused of nicking around 45 million pounds they should have paid to FIFA.

不过他最后仍有可能沦为瑞士政府&议事餐桌&上的一道早餐，因为这所有六个人都被指控把本应支付给国际足联的大约4500万英镑骗了个精光。