定时

As a school bell, teaching floor, lighting and the timing of a clearance, student dormitories and campus street lamp lights the timing switches, pumps and the start of the regular time control of water supply and so on.

如上下课打铃、教学楼照明的定时开与关、学生宿舍灯及校园路灯的定时开关、水泵的定时启动以及自来水供水时间控制等等。

Due to the complexity of the cell jitter, the NonSynchronous Tining Recovery methods are currently not mature With the emphasis being given to the Class A CBR traffic, this paper analyzes the performance of the queueing delay and cell jitter at the source node and intermediate nodes, and discusses the Source Timing Recovery at the destination node in ATM networks Firstly, this paper presents a description of the cell jitter of CBR traffic, and gives the definitions of two kinds of cell jitter regarding the Source Timing Recovery for CBR traffic Then, by using exact mathematical models and analysis methods, this paper analyzes the impact of the factors, such as the capacity of the queueing buffer, the randomness, the deterministic nature and the correlation in cell arrivals of the background traffic sources, on the queueing delay and cell jitter performance of the CBR traffic through Statistical Multiplexitng To obtain an insight into the power spectral distribution and look for better schemes for the depression and filtering of the cell jitter, within the analyses we succeed deriving the power spectrum of the cell jitter for CBR traffic Hence, not only the power spectral distribution of the cell jitter can in the frequency domain be qualitatively understood, but also can the rms (root-meansquare) value of the cell jitter be quantitatively obtained so as to more accurately measure the amplitude of the jitter In the end-to-end performance analysis of the queueing delay and cell jitter, we propose a kind of quasi-periodic cell stream model to characterize the jittered CBR traffic, and present an initial queueing analysis of the CBR traffic following such a model at a generic intermediate node Additionally, we briefly discuss the buildout/playout and Source Timing Recovery functions of the destination node Finally, regarding the Source Timing Recovery of CBR traffic, this paper systematically discusses several important principles of the cell jitter filtering and depression reported in the literature, introduces several implementation schemes of the Source Timing Recovery e.

由于信元抖动的复杂性，非同步定时恢复方法目前还很不成熟。本文针对A类CBR业务流在ATM网络源节点和中间节点的排队时延和信元抖动性能，以及在目的节点的源定时恢复问题作了较为全面的研究。首先，文中描述了CBR业务流的信元抖动，并具体地给出了两种与CBR业务源定时恢复有关的信元抖动的定义。然后，采用了精确的数学模型和分析方法，有针对性地分析了业务背景中信元到达的纯随机性、确定性和相关性以及排队缓存器容量等因素对CBR业务流经过统计复用后的排队时延和信元抖动性能的影响。为了了解信元抖动的功率频谱分布和寻求更好的抑制和滤除抖动的方法，在性能分析中，我们成功地完成了CBR业务流信元抖动的功率谱分析，使得不但可以从频域定性地认识信元抖动的能量分布特性，而且还可以定量地求出信元抖动的均方根值(rms：root-mean-square)，以更为准确地衡量抖动的大小。在CBR业务流的多节点端-端排队时延和信元抖动性能分析中，我们提出了一种准周期性(quasi-periodic)信元流模型来描述感染了信元抖动的CBR业务流，并基于这一模型进行了CBR业务流中间节点的初步排队分析。

The APIC's timer counter is 32 bits long, while the PIT's timer counter is 16 bits long; therefore, the local timer can be programmed to issue interrupts at very low frequencies (the counter stores the number of ticks that must elapse before the interrupt is issued).

APIC的定时器计数器是32位，而PIC的定时器计数器是16位；因此，可以对本地定时器编程来产生很低频率的中断计数器存放中断发生前必须经过的节拍数

It is determined as a result of heating facilities, regular and high-temperature heating. It operated hot water pipes so that in the 15 ℃---- 90 ℃ from time to time between the operation, resulting in accelerated aging boiler and pipe rust and scale in the United States on heating and heating from time to time out after a period of time. The purpose is to accelerate the pipeline of the scale and rust solid precipitation knot a few years later so easy to plug.

由于供热设施所决定，定时和高温供热，使热水管在15℃----90℃之间不定时运行，产生热胀冷缩加速老化，锅炉和管道中的铁锈和水垢在美日定时供热和取暖期过后停用时间，加速管道的水垢与铁锈的沉淀结固，几年后，使管理易产生堵塞。

Four 8-bit I/O Ports C Three 16-bit Timer/Counters C 256 Bytes Scratch Pad RAM C 8 Interrupt Sources with 4 Priority Levels C Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals High-speed Architecture C 10 to 40 MHz in Standard Mode 16K/32K Bytes On-Chip ROM Program T80C51RD2 ROMless Versions On-Chip 1024 bytes Expanded RAM C Software Selectable Size (0, 256, 512, 768, 1024 bytes) C 256 Bytes Selected at Reset for AT87C51RB2/RC2 Compatibility Keyboard Interrupt Interface on Port P1 8-bit Clock Prescaler 64K Program and Data Memory Spaces Improved X2 Mode with Independant Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels with: C High-speed Output C Compare/Capture C Pulse Width Modulator C Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes C Idle Mode C Power-down Mode C Power-off Flag Power Supply: 2.7V to 5.5V or 2.7V to 3.6V Temperature Ranges: Commercial (0 to +70C) and Industrial (-40C to +85C) Packages: PDIL40, PLCC44, VQFP44

四8位I / O端口C款三16位定时器/计数器 256字节RAM的便笺簿 8中断源4优先级和C双数据指针MOVX在缓变长内存/外设高速架构为C 10至40 MHz的标准模式16K/32K字节的片上ROM程序T80C51RD2无ROM版本片1024字节扩展RAMC软件可选尺寸（0，256， 512，768，1024字节）C选取在重置为AT87C51RB2/RC2兼容键盘中断接口与独立的选择港口小一8位时钟分频器64K的程序和数据存储器空间的改进X2模式的CPU和256字节每个外设可编程计数器5通道的阵列：C型高速输出C比较/脉宽调制器捕获看门狗定时器复位功能异步端口全双工增强型UART的波特率发生器的UART低EMI硬件看门狗定时器电源控制模式空闲模式C掉电模式C断电旗电源：2.7V至5.5V或2.7V至3.6V温度范围：商业（0到+70 C）和工业（- 40C至+85℃）封装：PDIL40，PLCC44，VQFP44

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Then, two methods of timing synchronization based on the cyclic prefix and pilot sequence were introduced, and a novel timing synchronization method based on pilot sequence was presented, which provided a correlation peak with pulse shape.

由于OFDM系统中的定时同步要求和无线定位中的测时测距在本质上是一致的，所以本文紧接着分析了基于循环前缀和导频序列的两种定时同步方法，并提出了一种新的基于导频序列的具有脉冲形状相关峰的定时同步方法。

According to the recommended frame structure of IEEE802.16,the independent correlation of multiple preambles and the unique words in data sequence were adopted in the algorithm,and the initial timing offset was estimated.

该算法基于IEEE802.16推荐的帧结构，利用多个前导字的独立互相关特性和数据序列中插入的独特字，对定时误差进行初始估计，并用内插环路进行定时估计误差的跟踪，获得定时同步结果。

Upon receipt of the second timing cell, the clock slave component will obtain its reception time and calculate a transmission delay based on the reception time and the timing information contained in the timing cells.

在收到第二定时信元时，从时钟部件将获得它的接收时间，并根据接收时间和包含在定时信元内的定时信息，计算传输延时。

It has been put forward that there exists single Ball point and double Ball points on the symmetrical connecting-rod curves of equilateral mechanisms.

从鲍尔点的形成原理出发，分析对称连杆曲线上鲍尔点的产生条件，提出等边机构的对称连杆曲线上有单鲍尔点和双鲍尔点。

The factory affiliated to the Group primarily manufactures multiple-purpose pincers, baking kits, knives, scissors, kitchenware, gardening tools and beauty care kits as well as other hardware tools, the annual production value of which reaches US$ 30 million dollars.

集团所属工厂主要生产多用钳、烤具、刀具、剪刀、厨具、花园工具、美容套等五金产品，年生产总值3000万美元，产品价廉物美、选料上乘、质量保证，深受国内外客户的青睐