存储单元

An arrangement of core storage in which the lowest numbered storage location is the successor of the highest numbered one.

磁芯存储器的一种编排方式，其中编号最低的存储单元是编号最高的存储单元的后续。

An arrangem t of core storage in which the lowest numbered storage location is the successor of the highest numbered one.

磁芯存储器的一种编排方式，其中编号最低的存储单元是编号最高的存储单元的后续。

It is because the spending of area and power of the SRAM memory cell takes a lot of percentage of the whole macro modules'. Using the α exponent MOSFET model to result the word line、bit line power model and delay model, together with the area model and analysis of the read/write reliability, we bring out a method to optimize the memory cell and evaluate the performance of the result.

特别对占模块面积和功耗绝大部分比例的SRAM存储单元做了细致的设计和仿真实验，通过采用α指数MOSFET模型推导出SRAM的字线、位线功耗模型和延迟模型，并配合存储单元的面积模型和读写可靠性分析，提出了一种优化存储体单元结构的方法，并对优化前后的性能进行了评估。

The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port.

所述电路包括：比较电路，用于输出第二端口地址总线信号对应的存储单元读屏蔽信号；非门，用于对第二端口地址总线信号对应的存储单元读屏蔽信号进行非运算；第一与门，第一与门的一路输入端接收非运算后的第二端口地址总线信号对应的存储单元读屏蔽信号，第一与门的另一路输入端接收第二端口的读使能信号，第一与门的输出端连接第二端口的读使能端。

The invention also discloses a dynamic skinning device, which includes a event type collection unit including a first monitor unit; a event type and treatment rule unit including a first storage unit, used to store the treatment rule corresponding to the dynamic skinning request; a searching unit including a first searching unit; a skin storage unit and a processing unit.

本发明还公开了一种动态换肤装置，该装置包括：事件类型收集单元，包括第一监测单元；事件类型与处理规则存储单元，包括第一存储单元；用于存储与动态换肤请求对应的处理规则；查找单元，包括第一查找单元；皮肤存储单元；处理单元。

The high speed multiplex first-in first-out storage structure includes at least two memory unit arrays, one integrated decoder circuit between the two memory unit arrays, one write-in control circuit over the decoder circuit, one read-out control circuit below the decoder circuit, two data buffers on the two memory unit arrays separately, two multiplex circuits and two output circuits below the two memory unit arrays separately, and one write-1 clock buffer and one read-out clock buffer over and below the decoder circuit separtely.

一种高速多路先进先出存储器结构，包括一至少两存储单元阵列、一位于至少两存储单元阵列中间的整体解码电路、分别位于整体解码电路的上下的一写入控制电路及一读出控制电路、分别位于至少两存储单元阵列上的两数据输入缓冲器以及依序位于两存储单元阵列下的两多工电路及两输出电路，在整体解码电路的上下分别设置一写入时钟缓冲器及一读出时钟缓冲器。

During the read operation, which connects a bit line or bit line bar to a memory cell, the charges stored in a memory cell may change the voltage level of the bit line.

在读取作业期间，将一位线或位线棒连接至一存储单元，存储于存储单元中的电荷可改变位线的电压电平。

In one embodiment, a memory device comprises a first memory cell and a second memory cell, wherein the first memory cell comprises a first transistor coupled to a bit line and the second memory cell comprises a second transistor coupled to a bit line bar.

在一实施例中，一种存储装置包含一第一存储单元及一第二存储单元，其中该第一存储单元包含一耦接至一位线的第一晶体管，而该第二存储单元包含一耦接至一位线棒的第二晶体管。

In the conventional CMAC learning scheme, the correcting amounts of errors are equally distributed into all addressed hypercubes, regardless the credibility of those hypercubes. The proposed improved learning approach uses the learned times of the addressed hypercubes as the credibility of the learned values.

在常规的CMAC中，误差的校正值被平均地分配给所有启动存储单元，而不管这些存储单元的可信度；在改进的CMAC中，利用激活单元先前学习次数作为可信度，其误差校正值与激活单元先前学习次数的负k次方成比例。

The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构，采用多元线性回归方法分析SRAM宏单元性能指标，采用解析方法分析控制电路延时，结合以上这两种方法建立嵌入式SRAM性能混合模型，该模型清晰划分两种建模方法的各自适用范围，提高了模型精度；其次以该混合模型为基础建立存储体性能目标函数，采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构，使之达到最优设计；最后综合考虑面积、功耗、速度以及可靠性等因素，建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程，分析了&读破坏&和&写破坏&的晶体管尺寸约束，优化了6-T存储单元尺寸，提高了嵌入式SRAM性能。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失