多电路的

By studying the internal structure and working principle of 555 timer, this paper introduces three typical circuits----Schmitt trigger, Bistable multivibrator and Astable multivibrator----which are composed by 555 timer. Furthermore, it explores the various applications of 555 timer in circuit designing through the expansion of the circuits and eventually same experience and methods offers in circuit designing by using 555 timer.

本文通过研究555定时器的内部结构和工作原理，介绍了其组成的施密特触发器，单稳态触发器和多谐振荡器等三个典型电路，并通过这些电路的扩展，探讨了555定时器在电路设计中的各种应用，由此得出用555定时器设计电路的经验和方法。

MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.

详细说明：多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。

A novel circuit with a narrow pulse driving structure is proposed for enhancing the noise immunity and improving the performance of wide fan-in dynamic circuits.

提出了一种利用窄脉冲发生器驱动输出级，以提高电路抗噪声能力，同时保持动态电路的高速特性的多输入动态逻辑电路。

The thesis contains five chapters. The first chapter summarizes the development and research of switched reluctance drive, discusses the main research direction, and explains the main work in this paper. In chapter 2, hardware system which includes the design of power converter and various control circuit is discussed. TMS320LF2407 DSP is used to design the hardware circuits of SRM control system, and design details including the current detection, position sensing, fault protection, speed detecting, keyboard and display etc. are provided. Because of the full use of the abundant peripheral resources of DSP, it comes to the aim simplifying the circuit structure and heightening the reliability. In chapter 3, the application of neural network on SRM control system is introduced, a new the application of neural network and the method of sampling is proposed and a simulation system based on Matlab/Simulink is established. Chapter 4 discusses the routine designing issue. Because the modularized programming method is adopted, and multi-interrupt processing technique is used, operation efficiency of the control software is highly raised. At last, the foregoing SRM control system is tested. Speed adjustment is realized, and other targets on the research and design of SRM control system are reached, which establishes a good foundation for further research.

本文共分五章，第一章概述了开关磁阻电机调速系统(Switched Reluctance Drive，简称SRD)及其发展和研究现状，论述了其主要研究方向，并说明了本文的主要工作；接下来的一章主要讨论了SRM的硬件系统，主要包括功率变换器的设计和各种控制电路的设计，本文以TMS320LF2407为核心设计了开关磁阻电机控制系统硬件电路，给出了包括电流检测、位置检测、故障保护、测速电路及键盘和显示电路等部分电路的详细设计，充分利用了DSP的丰富外设资源，达到了简化电路结构、提高运行可靠性的目的；第三章介绍了人工神经网络在开关磁阻电机控制系统中的应用，提出了一种新的应用方式(利用GPFN神经网络调节PI参数)以及如何采取样本，搭建了基于Matlab/Simulink的仿真系统；在第四章中，讨论了开关磁阻电机控制软件的设计，采用模块化编程方法，采用基于多中断的控制程序，提高了控制软件的效率；最后，对所设计的开关磁阻电机控制系统进行了实验，实现了电机调速，达到了开关磁阻电机控制系统研究和设计的预期目标，为更近一步研究打下了基础。

On the design of algorithms, a novel exact hierarchical delay analysis method for general circuits is proposed; based on the sensitization theorem for sequential circuits, an exact minimizing clocking method is proposed; based on Boolean process, a waveform simulation method considering interconnecting delay for logic circuit and a parallel waveform simulation method are proposed; a new method that transforms bit-level waveform polynomial to word-level polynomial model is proposed; a multiple valued synthesis algorithm based on multiple valued Boolean process and a wire-centered delay synthesis policy are proposed, in which timing planning, floorplanning, wire planning and optimal clock skew in early design are considered; a two-layers channel routing method for minimizing crosstalk under grid mode is proposed; based on the transition numbers theorems for waveform polynomial, a new method for generation of test with noise effects is proposed.

算法设计方面，提出了一种精确的通用电路层次化延时分析方法；基于时序电路的敏化定理提出时序电路最小时钟周期精确确定方法；提出基于Boolean过程论的考虑互连延迟的逻辑电路波形模拟方法，在分析了波形模拟适合并行化基础上，进一步提出一种并行波形模拟算法；提出一种将位级电路波形多项式描述转化成字级多项式描述的新方法；提出一种基于多值Boolean过程的多值电路综合算法以及一种将前期设计定时规划、前期设计的布局规划和线网结构化方法及低偏移的时钟分配等技术相结合的面向互连延时的综合策略；提出一种串绕最小化的网格模式下的双层通道布线方法；从波形多项式描述跳变数的定理出发提出了一种考虑噪声效应的测试生成新方法。

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.

提出了两种新的电路技术，在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流，并提高了电路的噪声容限。

The high speed multiplex first-in first-out storage structure includes at least two memory unit arrays, one integrated decoder circuit between the two memory unit arrays, one write-in control circuit over the decoder circuit, one read-out control circuit below the decoder circuit, two data buffers on the two memory unit arrays separately, two multiplex circuits and two output circuits below the two memory unit arrays separately, and one write-1 clock buffer and one read-out clock buffer over and below the decoder circuit separtely.

一种高速多路先进先出存储器结构，包括一至少两存储单元阵列、一位于至少两存储单元阵列中间的整体解码电路、分别位于整体解码电路的上下的一写入控制电路及一读出控制电路、分别位于至少两存储单元阵列上的两数据输入缓冲器以及依序位于两存储单元阵列下的两多工电路及两输出电路，在整体解码电路的上下分别设置一写入时钟缓冲器及一读出时钟缓冲器。

In order to be able to drive three separated speed controllers I wanted to be able to isolate the output stages of the controllers to prevent possible unpredictable high current loops between circuits, this also allows us to run one or multiple batteries safely so I experimented with some designs, The opto isolator device (4N35) can be inserted at various strategic parts of the circuit and in fact it is often at the front end at the receiver input but I chose to isolate just the output stage as I will be adding the other channel circuitry to the same receiver and battery eliminator circuit voltage rails.

在为了能够驱动器3分离速度控制器，我想能够隔离输出阶段的控制器，以防止可能出现难以预料的高电流环路之间的电路，这也使我们能够运行一个或多个电池安全，使i试行了一些设计，光电隔离器装置（ 4n35）可以插入各种战略的部分电路，并在事实上它往往是在前端，在接收器输入，但我选择了孤立刚输出阶段，因为我会加入其他渠道电路，同时接收器和电池消除电路的电压轨。

The equations for two-conductor coupled-line Marchand baluns are derived. The analysis and systematic design procedure for multi-conductor coupled-line Marchand baluns are also presented, and verified with a few fabricated multi-conductor coupled-line Marchand baluns. Two MMIC broadband diode frequency doublers using multi-conductor coupled-line Marchand baluns are implemented to demonstrate the design procedure of multi-conductor coupled-line Marchand baluns. The MMICs achieve miniature chip areas with broadband performances in millimeter-wave regime.

二金属耦合线马逊平衡不平衡转换器的方程式推导及多金属耦合线马逊平衡不平衡转换器的分析及系统化设计流程也在此论文中被提出，并且用许多实际制作的平衡不平衡转换器做验证，此外，两个微波单晶积体电路的宽频二极体倍频器包含多金属耦合线马逊平衡不平衡转换器也用来验证此多金属耦合线马逊平衡不平衡转换器的系统化设计流程，这两个微波单晶积体电路在毫米波的频段内都达到微小的晶片面积与宽频的响应。

An image display apparatus includes a display having data holding function, a vertical drive circuit sequentially and selectively scanning matrix form display elements, and a horizontal drive circuit writing a voltage among binary voltage preliminarily assigned depending upon the digital data of the image signal. The horizontal drive circuit and the vertical drive circuit are operated for performing selective scan of respective display element for at least m times in one frame period. The vertical drive circuit is constituted of n number of sequence circuits and logic operation circuits for outputs of the sequence circuits, where n is smaller than m, a period from inputting to the sequence circuit to outputting from the final stage being less than or equal to half of one frame period, and at least one of the sequence circuits being used with selectively inputting a plurality of inputs.

提供了一种图象显示器，其具有显示部，在矩阵上排列的象素内保有数据保持的功能，根据保持的数据进行显示；垂直驱动电路，对构成显示部的矩阵状显示器以每行按顺序作选择性扫描；以及水平驱动电路，对于由垂直驱动电路选择的行显示器件，根据应显示的图象信号数字数据，从预先分配的二进制电压中写入电压，并利用水平、垂直驱动电路，与应显示的图象信号同步，在1帧期间至少m次对各显示象素进行选择性操作，以此进行多色调显示，垂直驱动电路由满足n＜m的n个顺序电路和其输出的逻辑运算电路组成，顺序电路的输入从最后级输出为止的期间为1帧期间的1/2以下，并且，n个顺序电路的至少一个的输入是切换多个输入系统而使用。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。