多处理器

The versatile controller also includes a plurality of field device input/output ports communicatively connected to the processor, a configuration communication port connected to the processor and to the memory to enable the controller to be configured with the programming routines and a second communication port which enables a user interface to be intermittently connected to the controller to view information stored within the controller memory.

这个多功能的控制器也包含许多的通信地连接到这个处理器上的场装置输入/输入端口，还包含一个连接到处理器和存储器配置通信端口，使得控制器被编程程序和第二通信端口配置，这样使得用户接口能够被间歇地连接到控制器上来观察存储在控制器存储器中的信息。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

The 1MHz CPU might very well be faster, in practice, than the 2Mhz CPU - if it is more efficient or can process more tasks in each CPU cycle.

该处理器为1mhz很有可能更快，在实践中，比2mhz的中央处理器--如果这是更有效还是可以处理更多任务，在每个处理器周期。

Multi-master bus system. This could be two processors, or a processor and a DMA controller.

而面向不可缓存内存域的交换指令则有益于在多控制器系统中实现2个总线控制器（例如2个处理器，或一个处理器和一个DMA控制器）间同步。

The one kind of improved FWT algorithm for a finite sequence is proposed after studying theory of multiresolution analysis and analyzing technical characteristics of DSP.

在充分研究多分辨分析理论和分析信号处理器技术特点的基础上，针对DSP TMS320C3X的特点，提出了一种有限序列的FWT的改进算法，详细阐述了信号处理器上FWT的周期性扩展的实现问题，用DSPTMS320C3X汇编语言实现了改进的FWT算法。

Nevertheless, mobile phone of much money Android chose to use the Snapdragon processor that connects high, in the meantime, this processor also is to issue generation to be based on ARM/Linux to get online this one of choices.

不过，多款Android手机选择使用了高通的Snapdragon处理器，同时，该处理器也是下一代基于ARM/Linux上网本的选择之一。

On the basis of analysing the architectures that are made up of multiple microprocessors and their performances, a distributed hardware preprocessor for multiplex telemetry data streams is given in the paper.

在比较多机结构设备性能的基础上，给出了分布式、多数据流遥测数据预处理器的结构设计，该预处理器的各个数据流以多重计算方式构成，并兼有Wavefront阵列的特点。

Existing processors used for media processing and scientific computation, such as general purpose processor, DSP, vector microprocessor, special graphics processor and multiprocessor in chip etc, have their own limitations in applications.

现有的用于媒体处理和流式科学计算的处理器，如通用处理器、DSP、向量微处理器、专用图形处理器和片内多处理机等，都存在各自的局限性。

In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts by which any processor may interrupt itself or one or more other processors in the NUMA computer system.

除外部中断外，本发明的中断体系结构支持处理器间的中断，从而任何处理器可中断自己或者中断该NUMA计算机系统中的一个或多个其它处理器。

In order to reduce the conflict of L1P in CMT,we propose the policy of logic partition L1P Cache by n power of 2 and the competing loop lock.Now the fairness researchs always need single thread sample phase,we propose a novel fairness policy:FROCM,it doesn\'t need single thread sample phase.We propose ring cooperant L1 data Cache,which can reduce both the complexity of the design and the load of L2 Cache.We also propose a method to exchange threads dynamicly based on fast-shared data pool,it can detect the data consanguinity of two threads in real time and exchange them into one core rapidly.At last,we design and implement a dual-core and dual-thread VLIW prototype YHFT DSP/DS based on the above studies.In order to enhance the bandwidth of data path and reduce the delay of critical path delay of CMT processor,we design a 10R/6W register file full customly.

为了减小多线程运行时指令Cache的冲突，本文提出了二幂等分指令Cache策略和循环锁竞争机制；现有对CMT处理器公平性的研究常常需要中断其它线程进行单线程采样，针对这个问题本文提出了多线程公平性策略FROCM；本文提出了环形协同数据Cache结构，以解决CMT处理器中共享存储体负载重，冲突大的问题；本文还提出了基于快速共享数据缓冲池的线程动态交换技术；最后本文实现了一个双核同时多线程芯片原型YHFT DSP/DS。

However, as the name（read－only memory）implies, CD disks cannot be written onorchanged in any way.

然而，正如其名字所指出的那样，CD盘不能写，也不能用任何方式改变其内容。

Galvanizes steel pallet is mainly export which suits standard packing of European Union, the North America. galvanizes steel pallet is suitable to heavy rack. Pallet surface can design plate type, corrugated and the gap form, satisfies the different requirements.

镀锌钢托盘多用于出口，替代木托盘，免薰蒸，符合欧盟、北美各国对出口货物包装材料的法令要求；喷涂钢托盘适用于重载上货架之用，托盘表面根据需要制作成平板状、波纹状及间隔形式，满足不同的使用要求。