同步的

S98ZKA0336 VCD UP-GRADING CIRCUIT BOARD FOR A CD PLAYER OR CD-ROM 获证 US 发明 08/815309 5926606 2017/3/9 540,000 Nuvoton 让与 A VCD up-grading circuit board for a CD player or CD-ROM includes an MPEGdecoder, a microprocessor, a DRAM, an audio digital/analog converter, a TV encoder and a synchronous clock generator. The VCD up-grading circuit board for a CD player or CD-ROM is attached to the CD player or CD-ROM to allow the CD player or CD-ROM to play a VCD without additional connection between the VCD up-grading circuit board and the CD player.

S98ZKA0335 自动产生及校正系统同步时钟之影音光碟机升级板获证 TW 发明 86101019 90406 2017/1/29 460，000 Nuvoton 让与本发明系关於一种自动产生及校正系统同步时钟之影音光碟机升级板，尤指一种可附加於CD播放机内而升级为影音光碟播放机之升级用的电路板，此升级电路板为可解决传统升级电路与CD播放机之间同步讯号连接之不便性、易产生干扰与更改CD播放机原有线路所衍生之各项缺陷下，而为一种无需於其间额外连接同步时钟讯号，而在升级板上内建一同步时钟产生器，以随时监视CD播放机与MPEG解码器之左右声道取样时钟讯号之相位差而立即补正，即可达到令两者完全同步者。

The invention relates to an external synchronous TD-SCDMA cover network system, which comprises a main coverer and at least one driven coverer forming the cover network system; said main coverer, via synchronizing the TD-SCDMA descending signal of descending chain, outputs descending-ascending switch control signal to the main coverer, to obtain frame synchronization; sending the synchronous instruct signal to the driven coverer; obtaining the frame synchronization at the driven coverer, via external synchronous instruction signal, to complete the normal ascending-descending time slit switch.

本发明外同步TD-SCDMA覆盖网络系统，包括组成覆盖网络系统的主覆盖端和至少一个从覆盖端，所述主覆盖端通过对下行链路中的TD-SCDMA下行信号进行同步处理，向主覆盖端输出上下行切换控制信号，获得帧同步；并将同步指示信号发送至从覆盖端，从覆盖端根据外同步指示信号进一步获得帧同步，从而完成整个覆盖网络系统的正常上下行时隙切换。

To accelerate the widespread of Synchronous Chip Seal and improve the operation quality of Synchronous Chipsealer, key techniques which influence the operation quality is studied detailedly, including the control of distributing quality, the dynamics characteristics of hydraulic system and the spray characteristics of asphalt nozzle of Synchronous Chipsealer.1 The factors which influence Synchronous Chip Seal quality are studied. Fiducial probability of simultaneous distribution density is advised to be used in evaluating the distribution bias and standard deviation of asphalt and aggregates simultaneously, which is more advanced than the single index evaluation method used before.2 The volume efficiency formula of asphalt pump is revised after analyzing the data of volume efficiency with mathematical statistics, which is helpful to match the asphalt spray system and control the flow out of asphalt pump accurately. With equation deduction and experiment, dynamic of hydraulic system used in Synchronous Chipsealer is studied, which lay the theory foundation on improving the stability and efficiency from design and controlling.4 Simulation on hydraulic system used in Synchronous Chipsealer is done with AMESim; the results indicate that multi-circle parallel connected hydraulic system with constant pressure power is better than that with load-sensing pressure power at present, because the latter will oscillate when the multi circles work at the same time. This conclusion has been proved during the debug of Synchronous Chipsealer.5 Asphalt nozzle characteristics, such as flat jet shape, flow distribution, are studied with experiment, the results indicate that cross quality of asphalt distributing is not increased linearly follow the increase of fan overlap level, the best point usually exists between two whole overlap level, asphalt distributing quality is better than±4% at the 2.5 overlap level, meets the superior specified in standard; The distribution quality of Synchronous Chipsealer can be increased by spray asphalt of different flow rang with nozzle of different diameter

为了加快同步碎石封层技术的推广，提高同步碎石封层设备的作业质量，本文对同步碎石封层设备作业质量的影响因素与控制方法、液压系统的动力学特性和沥青喷嘴的喷洒特性等关键技术进行了深入细致的研究：1研究了影响同步碎石封层作业质量的因素，提出了采用联合密度分布置信概率对同步碎石封层中沥青洒布量和碎石撒布量的系统偏差和标准差指标进行综合评价的方法，克服了传统评价方法只能对单一指标进行评价的缺陷；2采用数理统计的方法，研究了沥青泵的容积效率特性，修正了沥青泵容积效率公式，为沥青喷洒系统的匹配和沥青泵出口流量的精确控制提供了依据；采用数理方程推导与试验相结合的方法，研究了同步碎石封层设备液压系统的动力学特性，为从设计和控制的角度提高同步碎石封层设备液压系统的稳定性和效率奠定了理论基础；3运用AMESim软件对采用负载敏感控制和恒压控制的两种同步碎石封层设备液压系统进行仿真，结果表明：负载敏感控制的并联液压系统在多回路同时工作时，由于液压泵排量控制参考压力不稳定，容易引发液压系统振荡，恒压控制的并联液压系统是目前技术条件下比较理想的同步碎石封层设备工作装置驱动方案；该结论亦通过同步碎石封层设备装机试验得到了验证。4采用试验的方法对沥青喷嘴的喷洒特性进行了研究，结果表明：沥青洒布的横向精度并不是随着喷洒扇面重叠度的增加线性增加，其最高点通常出现在二个重叠度之间的"半重叠位置"，"2.5重叠"洒布时，沥青的横向洒布精度≤±4%，可以达到国家相关标准中的优级标准；同步碎石封层设备还可以根据不同洒布量情况下的流量需求，采用不同通径的喷嘴进行喷洒，提高沥青洒布精度。

To solve the problem of channel with distortions, an adaptive circuit is configured by a new laddered method based on relevant articles, and simulation study was made on four dimensional Chua's chaos oscillator. The simulation results demonstrated that: synchronization of two chaotic oscillators can be achieved when adaptive circuit has adaptive capability. Synchronization of two chaotic oscillators cannot be achieved when adaptive circuit has no adaptive capability. Simulation studies were done for five scroll chaotic oscillators that achieve bond-orbit, coupling and pulse synchronization.

为了解决信道畸变问题，根据相关文献提出的梯度法，本文构造了一种自适应同步电路，并以四阶变型蔡氏混沌振荡电路为例进行仿真研究，仿真结果表明：当自适应同步电路具有自适应效应时能实现有噪声干扰情况下的两个混沌振荡电路的同步；若自适应同步电路没有自适应效应时，则不能使两个混沌振荡电路同步；以5涡卷混沌振荡电路为例用键波同步法、耦合同步法、脉冲同步法进行同步仿真研究。

For each type of testing, a necessary and sufficient condition is defined, under which a test sequence of an FSM is synchronizable. In this paper a new model—synchroniable digraph is proposed, which can judge whether there exist any synchronizable test sequence for a given specification without synchronization operation, and which can transform its nonsynchronizable test sequence to synchronizable test sequence if the answer is true. A method to judge how to add external synchronization operations in a nonsynchronizable test sequence to change it to synchroniable one is also proposed.

提出了一种新的同步测试序列生成模型——同步有向图，它可以判断一个给定的协议规格是否可以在不需要外部同步操作的情况下，产生同步测试序列；如果可以产生，则此生成模型可以将非同步测试序列转化为相应的同步测试序列；另外此生成模型还可以用来选择为测试系统增加外部同步通道的方法。

When the lock ring simultaneously with the question cone gear engagement ring gear, cone after contact friction moment in the role of the rapid speed of gear to reduce to synchronize with the speed equivalent to lock ring, the two synchronous rotation, relative to gear Central lock synchronization speed is zero, thus inertia torque also disappeared, then in force under the impetus of engagement sets unhindered and synchronization lock Gear engagement ring, and further engagement with the question of gear engagement ring gear and completed Shift process The topics mainly through the Pro / E synchronization software for the car to three-dimensional modeling structural design, and through the parameters of the design process to achieve its structure, and on this basis, the use of ANSYS FEM software structure of the typical synchronization And a finite element analysis, through structural analysis of its structural design is reasonable to assess and make recommendations to improve the design

当同步锁环内锥面与待接合齿轮齿圈外锥面接触后，在摩擦力矩的作用下齿轮转速迅速降低到与同步锁环转速相等，两者同步旋转，齿轮相对于同步锁环的转速为零，因而惯性力矩也同时消失，这时在作用力的推动下，接合套不受阻碍地与同步锁环齿圈接合，并进一步与待接合齿轮的齿圈接合而完成换档过程本课题主要是通过Pro/E软件对汽车同步器进行三维造型结构设计，并通过参数化实现其结构设计程序化，在此基础上，利用ANSYS有限元软件对典型同步器结构进行有限元计算与分析，通过结构分析对其结构设计的合理性作出评价并提出改进设计建议

Also, by using a novel offset architecture, as opposed to completely overlapped architecture, for the differential transmission pair, a 33% reduction of thickness is achieved in the design of a miniaturized common-mode filter with multi-layer LTCC technology. In view of increasing need of high-speed clock and data circuits to control their skew problems, a design of LTCC delay line is then conducted. To improve the waveform distortion associated with the microstrip/stripline-type meander delay line, a miniaturized high-frequency 3-D delay line with grounded guard traces is introduced. By means of 3-D structure, the 233 ps delay time, which requires extra board space amounting to a factor of 2.34 by stripline type meander delay line, can be shrunk into an EIA 1206 form factor.

为因应高速时脉及高速线路的不断发展，用於控制讯号、时脉同步的延迟线路需求日益增加，接著讨论的题目便是应用低温共烧陶瓷制程技术设计多层的延迟线路元件，为了改善在微带线/带线型折线式延迟线路波形失真的问题，论文中提出以接地的防护线来设计小型化的三维多层延迟线路元件，比较应用带线型折线式延迟线路和应用三维架构设计的延迟线路元件，同样提供233 ps的延迟时间，多层架构设计之延迟线路可缩小至EIA 1206 的尺寸，省下2.34倍的电路板面积。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Based on the return map and the principle of closed vectors, a new method is proposed to extract unstable periodic orbits embedded in chaotic attractors. As examples, the UPOs embedded in chaotic attractors of Logistic, Hénon and Lorenz are extracted respectively by this method. And our results of Skewed Hénon map also be compared with Nusse's. These results suggest that this method is valid for unstable periodic orbits from period one to period infinite of arbitrary dimension chaotic system. The dynamic considerations of spiking and UPO coding for individual neuron and neural system under external periodic and chaotic exciting stimulus also be studied in this dissertation. A lot of spiking phenomena, such as synchronization, period, and chaos appear alternatively with the changing of the stimulus frequency. For the small stimulus frequency the neuron could completely convey the periodic signal in synchronous anti-phase into interspike intervals sequences. For the slow time–scale chaotic input, the output two ISI sequences are reciprocally related to input signals, and their oscillation wave shape in time course can be derived from that of the input signals variation, furthermore, the similar input sequence and order of UPOs, distribution of LES and value of KYD remain in attractors reconstructed from ISI sequences.

发现周期信号在单个神经元传递过程中，随着激励频率的改变，神经元输出的峰峰间期interspike interval时间序列呈现出周期、混沌和准周期的交错变化，特别当外加激励信号频率较低时，周期信号可以通过神经元ISI序列以反相同步的周期运动形式传递下去；同时无论是周期还是混沌激励信号，在神经系统中的传递均与其自身强度和神经元之间的耦合强度的大小密切相关；快变时间尺度的混沌激励信号在耦合的神经系统传递过程中，会造成大量基本信息的丢失；而慢变时间尺度的混沌激励信号在神经系统传递中，它的非线性特征信息，如混沌吸引子、不稳定周期轨道、Lyapunov指数谱和分形维数，会通过系统输出的ISI序列部分地重现出来，如与输入慢变时间尺度的混沌激励信号相比，神经系统输出的ISI序列具有：相似几何形状的混沌吸引子、相近的Lyapunov指数谱和分形维数、局部结构相同的不稳定周期轨道的排列方式。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失