可中断的

The cost-benefit analysis of interruptible load is the basis of this research.

可中断负荷的成本效益分析是可中断负荷研究的基础。

ARM Series STM32F examples of NVIC application procedures, STM32F provide rich functionality to support the interruption, there are more than can be set interrupt priority level.

详细说明： STM32F系列ARM的NVIC应用例子程序，STM32F提供了丰富的中断功能支持，有多个可设定的中断优先级别。

An efficient method is developed for integrating interruptible electricity contracts in probabilistic production simulation of power systems.

提出了一种结合可中断电力合同交易的电力系统随机生产模拟方法，其中把可中断电力等效为具有随机停运特性的灵活发电资源。

So how to incentive and ensure the interruptible load participate in electricity market and enhance demand response becomes a key issue of ILM.

因此，如何激励与保障可中断负荷参与电力市场、增强用户的需求响应，成为电力市场下可中断负荷管理面临的关键问题。

On the basis of the principle of ILM the authors lead the interruptive load into power transmission congestion management and propose an optimal dispatchi...

作者从可中断负荷管理的原理出发，将可中断负荷引入到输电阻塞管理中，提出了通过潮流优化辅以可中断负荷控制的消除阻塞的最优调度模式。

In this model three objectives are included to eliminate the congestion, they are the least number of interruptive consumers, the least number of interruptive loads and the least total cost that the operator of autonomous system pays to interruptive loads.

给出了一种可中断负荷参与的阻塞管理多目标模型，该模型同时考虑了可中断负荷用户数最少、可中断负荷量最少和独立系统操作员支付给可中断负荷的总成本最少三个目标来消除阻塞。

In Chapter 2, we investigate preemptive machine covering problem.

第二章研究可中断的机器覆盖问题P

In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts by which any processor may interrupt itself or one or more other processors in the NUMA computer system.

除外部中断外，本发明的中断体系结构支持处理器间的中断，从而任何处理器可中断自己或者中断该NUMA计算机系统中的一个或多个其它处理器。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

After an interrupt is generated, the CPU compares the interrupt number (x8) against the size of the IDT -- stored in the interrupt descriptor cache register. If the INT# x 8 doesn't exceed the IDT size, then the interrupt is considered invokable, and the IDT base address is fetched from the descriptor cache; then the ISR's protected mode address is fetched from the IDT.

在产生一个中断之后， CPU 将会把中断号(乘以8)和 IDT 的长度进行比较（ IDT 的长度存储在中断描述符缓冲寄存器中），如果中断号乘以8之后的值没有超过 IDT 的长度，则该中断被认为是可调用的，然后将 IDT 的基址从中断描述符缓冲寄存器中取出； ISR 的保护模式帝制从 IDT 中取出。

Neither the killing of Mr Zarqawi nor any breakthrough on the political front will stop the insurgency and the fratricidal murders in their tracks.

在对危险的南部地区访问时，他斥责什叶派民兵领导人对中央集权的挑衅行为。

In fact,I've got him on the satellite mobile right now.

实际上 我们已接通卫星可视电话了