双端的

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Refers to the port in an FDDI topology which connects the incoming primary ring and the outgoing secondary ring of the FDDI dual ring. This port is part of the dual attachment station or a dual attachment concentrator.

指FDDI拓扑中的端口，连接FDDI双环结构中的输入主环和输出辅环。A端口是双连接站点或者双附加配置集中器的一部分。

Two special structural features of the sulfonium salt were proved to stabilize its corresponding ylide and depress the 2,3-sigma rearrangement. One is that there is a trimethylsilyl in the end of the allylic double band. This silicon atom can stabilize a α-carbon anion and the corresponding ylide. Another is that there is hydroxy group in the beta-position of sulfonium atom. The oxygen of this hydroxy group may stabilize the sulfonium cation.

为了稳定生成的烯丙基硫叶立德，并抑制它的2， 3-sigma 重排反应，在硫叶立德结构上做了两方面的考虑：一是在烯丙基双键的未端引入硅基，利用硅原子对 a -碳负离子的稳定作用来稳定烯丙基硫叶立德；二是在硫原子的 b -位引入羟基，利用羟基氧对硫正离子的作用来稳定硫叶立德。

Second, aminolysis of polystyrene and poly prepared by reversible addition-fragmentation chain transfer polymerization was investigated. The product of the former contains predominantly double molecular weight species by the formation of disulfide bond, whereas the latter formed coupled species which consequently cleaved to unimolecular weight species.

由RAFT聚合的机理可知，聚合最终得到的聚合物的结构包含双硫酯基团，它是聚合物链保持活性特征的重要体现，同时它为聚合物的端基官能化提供了一个重要的途径，其中氨解反应是一个被人们广泛采用的方法，它在很温和的条件下将端基去掉，同时还能将双硫酯端基变成硫醇端基。

CPU of airborne computer implements existing data acquisition of unpiloted vehicle with low efficiency. To improve the efficiency and to solve problems on reliability, real time and precision, the design of acquisition system based on DSP which can make a circuit acquisition for 54 channels data is put forward. After acquisition, the data can transfer between the system and CPU of airborne computer through dual-port RAM. The software and hardware methods to revise ADC on DSP are described. Evidences show that the system can meet with the flight control system on reliability, real time and precision.

现有无人飞行器数据采集均由机载计算机主处理器完成，效率较低，为了提高效率，解决数据采集的可靠性、实时性及精度等问题，设计了一种基于DSP处理器的数据采集系统，该数据采集系统能够对54路模拟量进行巡回采集，给出了系统的软硬件实现方法，在数据采集结束后，系统通过双端口RAM与机载计算机主处理器进行数据传递；为了提高DSP片内ADC的采集精度，给出了片内ADC的软硬件校正方法；实验证明，该系统具有较高的可靠性，能够满足飞行控制系统对传感器数据采集的实时性及精度要求。

By using a certain structure,the slip power can be feed backed through magnetical field.So the slip rings and brushes of the conventional EVT can be omitted,it will bring high reliability and less maintainability.

本结构较双机械端口电机的优点在于：无刷双馈双机械端口电机通过一定的电机结构，用磁场完成转差功率的回馈，取消了双机械端口电机中的滑环和电刷，增强了电机的稳定性，减少了维护工作。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

To compare with traditional EVT system, reserved some advantages, such as two rotors can run at different speed, and so on. The innovations of BL-DMPM included:① No brush and slide rings were needed, so simpled the structure of motor, and improved the reliability.② The rated speed of two rotors can be different according to selection of pole numbers, so the proposed motor was more appropriate than the traditional one when it was used in hybrid electrical vehicle, where large torque at low speed was needed.

它保留了传统双机械端口电机的主要优点，如两个机械端口可运行在不同转速和可无极连续变速等，而取消了传统双机械端口电机中的电刷和滑环，简化了电机结构，提高了可靠性，可以设计成使两个机械转子的额定转速相差很大，从而更适用于需要低速大力矩的混合动力汽车等场合。

The innovations of BL-DMPM included:① No brush and slide rings were needed,so simpled the structure of motor,and improved the reliability.② The rated speed of two rotors can be different according to selection of pole numbers,so the proposed motor was more appropriate than the traditional one when it was used in hybrid electrical vehicle,where large torque at low speed was needed.

它保留了传统双机械端口电机的主要优点，如两个机械端口可运行在不同转速和可无极连续变速等，而取消了传统双机械端口电机中的电刷和滑环，简化了电机结构，提高了可靠性，可以设计成使两个机械转子的额定转速相差很大，从而更适用于需要低速大力矩的混合动力汽车等场合。

I didn't watch TV last night, because it .

昨晚我没有看电视，因为电视机坏了。

Since this year, in a lot of villages of Beijing, TV of elevator liquid crystal was removed.

今年以来，在北京的很多小区里，电梯液晶电视被撤了下来。