加法器

Hold a carry bit from the last stage of the adder. It stores these values in

通常，检验寄存器从加法器的末级获得一个进位。

A digital integrator reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder.

减小电路面积和功耗的数字积分器只用一个加法器为一个抽取器实现两级积分。

And another use of FPGA is that provide DSP original data. DSP is used as digital filters used by sampling at the foreside and at the export correspondingly.The original data used by DSP is taken from the first adder in the circle. After the DSPs disposal,the output data are sent to guidance system.

总的说来，PGGA主要实现整个系统的时序控制和闭环回路，以及为DSP提供原始滤波数据；而DSP主要的工作是从PGGA那里取来第一个加法器输出的数据作为原始数据，再对数据进行滤波处理，最后的处理结果作为转速的信息送给捷联惯导系统。

The modification was nearly negligible in which the full adder cells are substituted by cells termed modified full adder and such design has not any additional critical paths inside the adders.

该设计改动微乎其微，通过将原有加法单元替换为一种改进的加法单元，对加法器原有关键通路无任何额外的时延影响。

According to the requirements for alternating current sampling, four feasible schemes (full-wave rectification, double 4051, raised analog ground and adder technique) are systematically contrasted in this dissertation. The hardware and software of this instrument are also analyzed in great detail.

本文围绕交流直接采样的技术要求，详细地对比分析了四种可行性设计方案，其中包括全波整流、双4051、模拟地抬高及加法器方式，并对其硬件实现和软件编程进行了详细的分析与论证。

A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.

本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。

This conclusion is more practical for the last stage of CSA array multiplier is the 4-bits CLA adder chain.

由于CSA阵列的最后一级为4位CLA加法器链，因此所得结果更具有实用性。

Operations of a 10-stage QSSERL inverter chain and a 2-bit QSSERL LLA fabricated in the charted 0.35μm standard CMOS technology has also been experimentally verified.

采用QSSERL设计的十级反向器链和两比特的对数超前进位加法器在charted0.35μm CMOS工艺下流片。

In order to find the effective length of the multiplier and multiplicand, we gathered detailed information of multiply operations from studying of the SPEC95 benchmark programs in advance.

根据此特性，我们提出了侦测前端零位元检测器和零加法器所构成非同步乘法加速器。

Residue Number System shows high performance of "area × power × delay" in VLSI design because of its parallel characteristic.

余数系统中的并行处理特性在VLSI系统中表现了很好的"面积×功耗×时延"特性，而模加法器作为构建RNS系统的基本单元之一，其复杂度在很大程度上决定了余数系统的性能。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。