查询词典 vin

To know this for sure, look into some VIN decoders or online services such as CarFax History Reports.

知道这肯定，看看一些VIn或解码器或上网服务，例如历史carfax报告。

S1 is then changed to position 1. The voltage stored on C1 is inserted between the output and inverting input of the amplifier and the output of the amplifier changes by VIN to maintain the amplifier input at the input offset voltage. The output then changes from (VOS + IbiasR2) to (VIN + IbiasR2) as S1 is changed from position 2 to position 1. Amplifier bias current is supplied through R2 from the output of the amplifier or from C2 when S1 is in position 2 and position 1 respectively. R3 serves to reduce the offset at the amplifier output if the amplifier must have maximum linear range or if it is desired to DC couple the amplifier.

接着 S1 拨到位置 1，使 C1 的电压加在放大器的输出端和反相输入端之间，(由于电容端电压不能突变，所以)输出端的电压将产生大小等于 VIN 的变化，使放大器输入端维持输入失调电压，即当开关 S1 从位置 2 拨到位置 1 时，输出端电压将从(VOS + IbiasR2)变为(VIN + IbiasR2)。S1 处于位置 2 时，放大器的偏置电流是由输出端经电阻 R2 提供的，当 S1 转向位置 1 时则由 C2 提供。R3 的作用是降低输出失调电压，如果要求放大器具有最大的线性范围，或者采用直流耦合，就应该使用该电容。

The Inhibit control (pin 3) has an internal pull-up to Vin, and if left open-circuit the module will operate when input power is applied.

抑制控制（引脚3）有一个内部上拉至VIN，如果离开了开路模块将输入功率运行时应用。

Pulse width generator 404 delays the output signal VIN of NAND gate 403 to generate an output signal VOUT.

脉冲宽度发生器404延迟NAND门403的输出信号VIN从而生成输出信号VOUT。

Inverters 505 and 506 are coupled together in series between NAND gate 403 at VIN and a second input of multiplexer 510 to form a second delay path.

反相器505和506在NAND门403的VIN和乘法器510的第二输入端之间串联耦合到一起从而形成第二延迟路径。

Inverters 501-504 are coupled together in series between NAND gate 403 at VIN and a first input of multiplexer 510 to form a first delay path.

反相器501-504在NAND门403的VIN和乘法器510的第一输入端之间串联耦合到一起从而形成第一延迟路径。

After the UP and DN signals both become a logic high at the same time, NAND gate 403 generates a falling edge on VIN.

在UP和DN信号同时都变为逻辑高电平后，NAND门403产生VIN的下降沿。

After the UP and DN signals transition to a logic low, NAND gate 403 generates a rising edge in VIN, and pulse width generator 404 generates a rising edge in VOUT a delayed period of time later.

在UP和DN信号转换到逻辑低电平后，NAND门403在VIN中生成上升沿，且脉冲宽度发生器404在延迟时间段后在VOUT中生成上升沿。

NAND gate 403 is a logic gate that performs a NAND Boolean logic function on the UP and DN signals to generate a voltage signal VIN.

NAND门403是对UP和DN信号执行NAND布尔逻辑功能以生成电压信号VIN的逻辑门。

The time delay (T1) that NAND gate 403 takes to generate a falling edge in VIN plus the time delay (T2) that a falling edge in VIN takes to propagate through pulse width generator 404 to VOUT plus the time delay (T3) for flip-flops 401 and 402 to generate falling edges in the UP and DN signals after a falling edge in VOUT equal the minimum pulse width of the UP and DN signals (T1+T2+T3=MPW).

NAND门403在VIN中生成下降沿的时间延迟(T1)加上VIN中的下降沿通过脉冲宽度发生器404传递到VOUT的时间延迟(T2)再加上触发器401和402在VOUT中的下降沿后在UP和DN信号中生成下降沿的时间延迟(T3)等于UP和DN信号的最小脉冲宽度，即(T1+T2+T3=MPW)。

The concept of equivalent rotationally rigidity is offered and the formula of rotationally rigidity is obtained.

主要做了如下几个方面的工作：对伸臂位于顶部的单层框架—筒体模型进行分析，提出了等效转动约束的概念和转动约束刚度的表达式。

Male cats normally do not need aftercare with the exception of the night after the anesthetic.

男猫通常不需要善后除了晚上的麻醉。