查询词典 video buffer

And the on chip data memory is byte addressable double data buffer structure, so that the unaligned data load and store can be supported and data can be prepared by DMA engine concurrently with computing.Finally, a video application specific SoC platform design and optimize. In video SoC platform, the embedded RISC processor and EDO-SIMD video processing engine were integrated with the DMA and LCDC etc. IP based on AMBA SoC interconnection and dedicated communication channel.

在片上数据存储的设计中，采用了Byte可寻址的双data-buffer的策略，既可以支持内存的非对齐访问，又可通过DMA并发完成数据的搬运。3视频处理SoC平台的设计基于AMBA总线和主要处理引擎间专用信道的SoC互连，以嵌入式RISC处理器和基于EDO-SIMD指令体系的视频处理擎为核心，配以DMA和内存控制器等外设，构成了一个基本的异构多核视频处理SoC平台原型。

Video capture of the image stored in the buffer, the buffer from where calls and handle images.

视频采集的图像存放在buffer里，可以从buffer里调用图像并进行处理。

Video buffer controller is one of the core subsystems of the video system center of electronic endoscope.

视频缓存控制器是电子内窥镜视频处理系统的核心之一，也是影响视频图像实时处理速度的瓶颈之一。

The video buffer is then cleared by painting a black rectangle to the entire screen using the SDL_FillRect function.

视频缓冲区，然后清除画一个黑色矩形整个屏幕使用SDL_FillRect功能。

Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or C1 voltage buffer.

根据不同的外部连接，内部电阻网络可以用来提供任何视频缓冲器的2 +1或1或C1的电压缓冲器增益固定增益。

Manual Video buffer size support.

手册视频缓冲区大小的支持。

Why audio buffer needs only one stage while video buffer needs two stages for amplification?

为何音频电路仅需要单级放大电路，而影像电路必须两级反向。

Screen displays, an element of additional information stored with each character in the video buffer of a video adapter running in character mode.

2，在屏幕显示中，当视频示配器运行于字符模式下时，与视频缓冲区中每个字符一起存储的一个额外信息元素。

Sometimes a video overlay buffer is premultiplied by alpha or premapped via a lookup table, in which case it's referred to as a "shaped" video buffer.

有时一个视频叠图缓冲区要预先乘以 a ，或者预先借助速查表进行映射，在这种情况下，它被称为一个"经过整形的"视频缓冲区。

To realize high-speed real-time processing for high-definition and low-distortion endoscopic image, this thesis introduces the FPGA design of video buffer controller for high definition electronic endoscope.

本课题针对现代电子内窥镜在视频图像的高清晰度、低失真以及高速实时处理等方面不断增长的需求，设计实现了基于FPGA的高清电子内窥镜视频缓存控制器。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。