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transistor相关的网络例句

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与 transistor 相关的网络例句 [注:此内容来源于网络,仅供参考]

IC2 is N1P2N2 transistor base current, it makes its collector current IC1 and emitter current IA increased.

IC2是N1P2N2晶体管的基极电流,它又使得其集电极电流IC1和发射极电流IA增加。

We know that in a transistor operating in its active mode, collector current is equal to base current multiplied by the ratio β.

我们知道,当晶体管工作在放大区时,集电极电流等于基极电流乘以系数β。

We've seen already how maintaining a constant base current through an active transistor results in the regulation of collector current, according to the β ratio.

我们已经看到有源晶体管的恒定的基极电流是如何以系数β控制集电极电流的。

The circuits that can be analyzed are limited to a basic amplifier and a single transistor with a common emitter.

可以被分析的电路限于基本的放大器和带公共发射器的晶体管。

In this paper the relationships between small-signal h-parameters and elements of the natural equivalent circuit of the common emitter configuration of junction transistor s are studied.

本文研究面结合型晶体管共发射极线路的小讯号h参数与自然等效线路中元件的关系。

In common emitter configuration and class C operation, the SiGe heterojunction bipolar transistor with continuous wave output power of 5W and collector conversion efficien...

在共射结构C类工作状态下,SiGe异质结双极晶体管工作在900MHz时,连续波输出功率为5W,集电极转化效率为63%,功率增益为7.4dB。

With this mode of working the base-emitter circuit is the input side;and the emitter through base to collector circuit the output side.although these have a common path through base and emitter, the two circuit are effectively separated by the fast that as far as polarity of the base circuit is concerned,the base and upper half of the transistor are connected as a reverse biased diode.hence there is no current flow from the base circuit into the collector circuit.

这一工作模式下,基极-发射极电路是输入端,发射极通过基极,再到集电极电路的输出端。虽然它们都有一个共同的路径通过基极和发射极,这两个电路是通过和基极电路相关的尽可能的有效快速分离开的,基极和基极以上的一半以上的晶体管作为一个反偏二极管与之相连接。

AMPLIFIER input bias current, a function of TRANSISTOR current gain, is also a function of the applied input common-mode voltage.

放大器的输入偏置电流,晶体管的电流放大作用,也具有加到输入共模电压的作用。

The integrated circuit also has at least a second current feeding circuit having an output connected to the feeding point for the first current feeding circuit, a feeding point connectable to a feeding voltage, and a control input for controlling the programming of the NPN-transistor.

所述集成电路还包括至少一第二电流馈电电路,所述第二电流馈电电路具有一连接至所述第一电流馈电电路的所述馈电点的输出端、一可连接至一馈电电压的馈电点及一用于控制对所述NPN晶体管进行所述编程的控制输入端。

After reviewing lots of previous work on cell layout generation and standard-cell and BBL placement and routing technique, algorithms for transistor placement and intra-cell routing in cell layout generation, timing-driven standard-cell placement, multi-layer detailed area routing and multi-layer constrained via minimization are presented and implemented.

论文在较为深入研究和总结国内外有关单元版图自动生成及集成电路布局布线技术方面研究成果的基础上,对标准单元版图自动生成技术中单元内晶体管布局和单元内布线、时延驱动的标准单元布局、多层金属工艺的区域详细布线及多层布线通孔最少化进行算法研究、设计和实现。

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