查询词典 single channel

It is still needed to do some work to determine the deformation parameter β2 for light odd-odd nucleus, like 6Li and to calculate all reaction channels by means of CDCC code simultaneously. It is important to measure the exclusive angular distributions of breakup fragments.In theory, the coupling channel equations have been deduced from one-dimensional to multi-dimensional barrier tunneling. The couplings between the entrance channel and the other channels have appreciable effects on sub-barrier fusion cross section. Instead of single fusion barrier,these couplings lead to a distribution of fusion barrier Dfus.

描述了已有理论，从简单的一维势垒穿透模型出发，引入多维势垒穿透和耦合道模型，证明入射道相对运动与碰撞核各种自由度的耦合导致熔合势垒的劈裂，较低的势垒有利于垒下熔合截面增强；给出了从熔合激发函数抽取势垒分布及从背角准弹激发函数抽取势垒分布的理论依据，以及它们的优缺点。

In this paper, we propose a channel management protocol for multi-channel, single-radio 802.11-based wireless mesh networks.

在本篇论文中，我们提出了一个在单一天线多频道的无线网状网路环境下的频道管理协定。

The water molecules inside the nanoscale water channel with the suitable radius are in the single-file arrangement, and moved concertedly in the channel.

被约束在纳米通道中以及处于固液介面上的水分子，展现出了许多与宏观不一样的特殊行为。

The evolvement of Diffluence River is the more complicated than Single River, because the diversion"s thing is changed with channel"s distortion. The river diversion is the general reflection of a good many factors, which mutually influence and adjust. In particular, when main channel occurs scouring-silting change, which causes the movement of water, sediment, and river bed in river system, the diversion will more be changed, with the study on division of discharge and sediment been further into, some practical engineering problem are solved.

目前，在对河道分流的认识与治理开发上虽取得了不少成绩，但随着社会经济的发展，人们对分流河道演变规律的认识与治理要求越来越高，随着人类对河流改造活动的加剧，河道的水沙条件可能发生急剧的改变，这些变化有可能使分流分沙的缓慢变化加剧，甚至改变原来的分流规律，许多研究者对分流分沙进行了较深入的研究，并能较好地解决了工程实际问题。

Thus, the output will always be driven by a single transistor, either P- channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Fig. 3.4 CMOS NAND gate One of the main problems with CMOS gates is their speed. They cannot operate very quickly, because of their inherent input capacitance. B-series devices help to overcome these 24 Lesson 3 CMOS Logic Circuit 25 limitations to some extent, by providing uniform output current, and by switching output states more rapidly, even if the input signals are changing more slowly. Note that we haven't gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits to prevent input voltages from becoming too high. [3] However, these protection circuits don't affect the logical behavior of the gates, so we won't go into the details here. New Words and Phrases 1. CMOS abbr.

略语互补金属氧化物半导体(complementary metallic oxide semiconductor)逻辑，逻辑学，逻辑性，推理方法补充的，补足的，互补的电池供电的门电路，逻辑门，闸门，控制栅，大门，通道，门口，入口伏特，环骑，闪避基础的，基本的，主要的基本原则，基本原理增强型金属氧化物半导体场效应晶体管(metallic oxide semiconductor field effect transistor)反相器，反用换流器，变极器来源，水源，消息来源，原始资料，发起者源，源极排水沟，消耗，排水漏极排出，喝干，耗尽排水，流干，耗尽相同的，相配的，匹配的匹配有效地，有力地，事实上，实际上无限的东西无穷大无穷的，无限的，无数的，极大的接地的正向偏置的，正偏的或非 25 2。

However, the role of inactivation gate of sodium channel is not clear. In present study, single fibre recording in vivo from dorsal root on chronically compressed DRG model was used. We analyzed the characters of ISI series of oscillation firing of type A neurons induced by veratridine, an inhibitor of inactivation gate of sodium channel.

本研究在大鼠背根节慢性压迫模型上，利用在体单纤维记录方法，观察与分析Na通道失活门抑制剂藜芦碱引起受损背根节A类神经元放电ISI序列发生的变化特征，为了解Na通道失活门与放电型式的关系以及进一步探索放电时间型式与疼痛的关系奠定基础。

Aimed at the complexity of fluvial strata, such measures as well cyclical comparison, step control and geological analysis of reference beds have been applied. Moreover the paper has developed a set of methods the techniques to extract the parameters controlling the formation of intra-sandbody thin interbeds. The present study has examined how thin interbeds affect the frame property and heterogeneity of individual sandbodies; revealed the permeability space distribution mode of meandering distributary channel's single side lithosomic body and straight distributary channel's aggrading lithosomic body. Through applying the distributary channel sandbody structural unit classifying and identifying method achievement, some horizontal wells have been deployed to dig the residual oil in the top of hick pay zone in the xing8-9 area, which shows better effect after they have been put into production.

针对分流河流砂体沉积特点采用了旋回对比、分级控制、不同相带区别对待的单油层对比方法；利用取心井、对子井等资料研究形成了分流河道砂体内部结构单元的倾角、倾向、规模等参数的提取方法；搞清了内部结构单元对单一砂体内非均质性的控制作用，建立了分流平原相单一点坝侧积体及顺直型分流河道单一加积体层内渗透率分布模式及剩余油分布模式，应用分流河道砂体结构单元划分方法识别研究成果，在杏树岗油田杏八九区纯油区部署了水平井，投产后见到了较好的厚油层顶部剩余油挖潜效果。

Based on the analysis of physics course of heat transfer, the mathematical model of single-phase flow in the rectangular narrow channel is proposed. And the boundary conditions are given to get the unique numerical result. The finite volume method is used to found the discrete scheme of equations. According to the flow of SIMPLER arithmetic, the computing program is developed and the correctness of program is validated.Then the program is used to solve the problem of flow and heat transfer in rectangular narrow channel.The stable two dimension velocity and temperature fields in rectangular narrow channel and plate fuel are obtained.

在明确窄缝流道及燃料板换热物理过程的基础上，建立了描述矩形窄缝内单相流动与换热问题的数学模型，并给出了合理的边值条件；然后利用有限容积法对方程进行离散，根据SIMPLER算法的流程编制了模型求解程序；在验证程序正确性的基础上，对矩形窄缝流动与换热问题进行了求解，得到了矩形窄缝流道和板状燃料元件内部温度场、速度场的二维分布。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Neither the killing of Mr Zarqawi nor any breakthrough on the political front will stop the insurgency and the fratricidal murders in their tracks.

在对危险的南部地区访问时，他斥责什叶派民兵领导人对中央集权的挑衅行为。

In fact,I've got him on the satellite mobile right now.

实际上 我们已接通卫星可视电话了