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signal clock相关的网络例句

查询词典 signal clock

与 signal clock 相关的网络例句 [注:此内容来源于网络,仅供参考]

The commutations follow the level change of a special synchro signal, called "clock".

所有的转变都是遵循一个特别的同步讯号,称为"时钟"。

At the last of chapter 7, a new improved measurement method using TIA is introduced high frequency clock signal.

在论文的最后一章中介绍了一个用于完成对jitter的性质进行时间间隔分析测试与验证的系统的设计。

C Supports both Firmware Hub and LPC Memory Read and Write Cycles Auto-detection of FWH and LPC Memory Cycles C Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets C Can Be Used as LPC Flash for Non-Intel Chipsets Flexible, Optimized Sectoring for BIOS Applications C 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector, Three 64-Kbyte Sectors C Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing Two Configurable Interfaces C FWH/LPC Interface for In-System Operation C Address/Address Multiplexed Interface for Programming during Manufacturing FWH/LPC Interface C Operates with the 33 MHz PCI Bus Clock C 5-signal Communication Interface Supporting Byte Reads and Writes C Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors C Five General-purpose Input Pins for System Design Flexibility C Identification Pins for Multiple Device Selection C Sector Locking Registers for Individual Sector Read and Write Protection A/A Mux Interface C 11-pin Multiplexed Address and 8-pin Data Interface C Facilitates Fast In-System or Out-of-System Programming Single Voltage Operation C 3.0V to 3.6V Supply Voltage for Read and Write Operations Industry-Standard Package Options C 32-lead PLCC C 40-lead TSOP

0第0页,本页显示记录0-0,共0条记录分0页显示C支持两种固件中心和LPC内存读取和写入周期自动的FWH和LPC的记忆圈C检测可以用于英特尔8xx系列,E7xxx,E8xxx系列芯片组和C可以用作FWH与至于非英特尔芯片组的BIOS应用柔性优化扇区开放16字节热门引导扇区,两个8 - Kbyte的,一个32字节部门,3个64 - Kbyte的C或存储阵列,线性预测编码闪光可分为四个统一为两个可配置的接口擦除的FWH / LPC接口为64 - Kbyte的行业,系统运行C地址/地址多路复用在制造过程中用于编程接口的FWH /线性预测编码界面C与33 MHz的PCI总线时钟 5信号通信接口进行操作,支持字节读取和写入引导扇区的顶部和WP C两硬件写保护引脚:任务型为所有其他部门 5个通用输入的系统设计的灵活性识别的多种设备选型部门登记销锁定为个别部门读取和写保护的A /阿复用界面C 11引脚复用引脚地址和8引脚的数据界面C促进快速系统内或外的系统编程的单电压3.0V至3.6V的操作供应的读取和写入操作业界标准的封装选项电压 32 -引脚PLCC 40引脚的TSOP

However, the host must provide a clock edge for the card to turn off its busy signal.

然而,主控制器必须要提供一个时钟沿给 SD 卡来关掉它的"忙"信号。

Styling / Convenience Engine Trim Black powder-coated with Wrinkle-Black treatment Exhaust System Chrome, staggered shorty duals Foot Supports and Controls Mid-mounted rider footpegs with brake and shift levers; standard passenger footpegs Handlebars Stainless steel, wide, dirt-track inspired Seat One-piece, two-up Sportster classic Instruments Electronic speedometer with odometer, time-of-day clock on odometer, dual resettable tripmeter, fuel gauge with low fuel warning light, low oil pressure indicator light, diagnostics readout, LED lights, tachometer Hazard Warning Integrated into turn signal controls Smart Security System Optional, next-generation hands-free security fob; operates based on proximity to vehicle

称呼/便利引擎修剪黑色粉末上漆与皱痕黑治疗排气系统镀铬物,摇摆的shorty 双倍脚支持和控制中间登上的车手footpegs 与闸和转移杠杆;标准乘客footpegs 把手不锈钢,宽,土轨道启发了位子单件, two-up Sportster 经典仪器电子车速表与测路器, time-of-day 时钟在测路器,双重resettable tripmeter,燃料测量仪以低燃料警告灯,低油压显示灯,诊断读出, LED 点燃,车头表危险警告集成轮信号控制聪明的保安系统任意,下一代没有雇工的安全fob;操作根据与车的接近度

The design of accelerometer/angulometer is based on MSP430FW425 microcontroller and ADXL202 accelerate sensor. Protel DXP is used in circuit design, which completes the schematic and PCB design of modules including the clock circuit, the filtering circuit, the power supply circuit, the communication circuit between MSP430 and PC, ADXL202 collecting signal circuit and LCD display circuit.

硬件部分采用Protel DXP开发平台完成了系统的时钟电路、滤波电路、电源电路、MSP430 与PC机之间通信电路、ADXL202传感器电路、LCD显示电路等的电路原理图和PCB板图设计,完成了硬件实物制作。

SteadyClock has originally been developed to gain a stable and clean clock from the heavily jittery MADI data signal.

SteadyClock 最初是为了增强 MADI 数字信号中那带有严重的 jitter 问题的时钟的稳定和清洁而开发的。

Because of the features of switch capacitor we should adopted nonoverlapping clock signal if we want to guarantee charge completely through the switching of power MOSFET.

由于开关电容的充放电特点,为确定电容时间常数,采用非交叠时钟控制信号避免了由于时钟交叠而造成的当电容充电还未完成即对下一级电容进行放电的现象。

Besides,the characters and functions of the chips are also analyzed and depicted. The CPU is TMS320VC5409, the hardware is designed according to the function modules, these modules are power supply module、signal opsonic module、data processing module、time clock module、UART module and pulse output module.

系统的核心是数字信号处理器的TMS320VC5409,以模块化的设计方法将仪表的硬件按功能分为几大模块进行设计,分别为:电源模块、输入调理模块、数据处理模块、时钟模块、通信模块、脉冲输出模块。

The phase of the clock signal inputted to a panel is made regulatable on the outside in such a manner that the delay amount of the sampling pulses is compensated based on the feedback pulse.

根据反馈脉冲,可在外部调节输入面板的时钟信号相位,以补偿采样脉冲的延迟量。

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在对危险的南部地区访问时,他斥责什叶派民兵领导人对中央集权的挑衅行为。

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