查询词典 signal clock

The reference clock signal RCLK leads the feedback clock signal FCLK, generating a series of pulses in the DN signal and longer pulses in the UP signal.

在图3中，基准时钟信号RCLK引导反馈时钟信号FCLK，在DN信号中生成系列脉冲，在UP信号中生成较长的脉冲。

By utilizing the cross-gain modulation effect and the period-one oscillation harmonic frequency-locked in an optically injected semiconductor laser, we can extract the wavelength conversional individual channel optical clock from the optical-time-division-multiplexing signal. In a FP-LD, we numerically simulate the extraction of 20 GHz optical clock at 1550 nm from the 2×20 Gb/s OTDM signal at 1555 nm, and experimentally obtain the -105 dBc/Hz phase noise frequency division clock of 12.36 GHz to 6.18 GHz with simultaneous wavelength conversion from 1550.24 nm to 1545.91 nm.

采用一个FP半导体激光器作为全光分路时钟提取及波长转换器，数值模拟实现了从波长为1555 nm、速率为2×20 Gb/s的光时分复用信号中提取出波长转换为1550 nm、重复频率为20 GHz的分路光时钟，实验完成了从波长为1550.24 nm、重复频率为12.36 GHz光脉冲信号中提取出相位噪声为-105 dBc/Hz的波长为1545.91 nm、重复频率6.18 GHz的分频光时钟。

A DPC ( 300 ) includes: a frequency source ( 310 ) for generating a clock signal; a delay line ( 320 ) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device ( 330 ) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices ( 500, 510, 520 ) and a combining network.

DPC(300)包括：频率源(310)，用于产生时钟信号；延迟线(320)，用于接收时钟信号并在输出抽头产生相移时钟信号；数字控制器件(330)，用于产生控制信号；以及开窗口与选择电路，用于产生输出信号，包括：时序逻辑器件(500、510、520)和组合网络。

Over their heads, there are tele-communication tower and time signal clock of the city.

窗口下，会有几个摊点卖着西瓜什么的，在他们的头顶方向，是电信塔楼和城市报时钟。

Its highly efficient jitter suppression enables ADI-648, HDSP 9632 and HDSP MADI to refresh and clean up any clock signal, and to provide the clock signal as reference clock at the word clock output.

它具有非常有效的 jitter 抑制能力，能让 ADI-648、HDSP 9632 和 HDSP MADI（这几个都是具备了 SteadyClock 技术的产品）把任何时钟信号都&清洗干净&，并且提供了等同于字时钟输出的时钟信号。

In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The stability of this sampling clock affects the display image quality directly. If the pixel clock is not stable, the display image will be glittering or jittering.

在本论文中，我们提出一个高频率倍数的全数位式锁相回路，此电路可应用於视讯系统中的时脉产生器，其主要功能是接收显示卡发出的水平同步讯号，并依据使用者设定的萤幕解析度，产生高频像素时脉来撷取视讯讯号资料，取样点的稳定度直接影响到显示画面的品质，若是像素时脉不稳定，则显示画面会闪烁或抖动。

Clock master to be due to a certain frequency in order to work with the FLASH communication should * transmit clock signal, so if there is no clock signal, control will not work.

时钟，因主控要在一定频率下才能工作，跟FLASH通信也要*时钟信号进行传输，所以如果时钟信号没有，主控一定不会工作的。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

A method for use in a DPC includes: receiving ( 400 ) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting ( 410 ) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating ( 420 ) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

在DPC内使用的方法包括：基于期望的输出信号接收(400)用于识别该延迟线上的第一输出抽头的控制信号；根据该控制信号，在该延迟线上至少选择(410)两个输出抽头，以至少接收两个不同相移时钟信号；以及根据该控制信号和收到的基本上是期望的输出信号的相移时钟信号，产生(420)输出信号。

Neither the killing of Mr Zarqawi nor any breakthrough on the political front will stop the insurgency and the fratricidal murders in their tracks.

在对危险的南部地区访问时，他斥责什叶派民兵领导人对中央集权的挑衅行为。

In fact,I've got him on the satellite mobile right now.

实际上 我们已接通卫星可视电话了