查询词典 rising edge

The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE .

写入周期是由持续教育部门和较早兴起的边缘终止/或年度预算案，否则我们。

Data is loaded into the internal 16-bit Shift register on CLK's rising edge.

在CLK的上升沿，数据被移入内部移位寄存器。

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CSis low.

EOC 的上升沿，转换结果的第一位在DATA OUT 引脚上等待CS 变为低时输出。

The rising edge of the pulse usually evolves in field distribution from far to near gauss distribution.

研究表明，脉冲产生时的泵浦光影响因子可以反映这种倏变现象的强烈程度。

Trigger control circuit in accordance with pulse phase and input along the angle of the trigger value, the corresponding time delay after the rising edge of trigger pulse, open SCR, and in the corresponding half-cycle before the end of hair falling edge trigger pulse, turn-off thyristor, for the next half cycle of the trigger ready.

触发控制电路根据鉴相脉冲沿和输入的触发角数值，延迟相应时间后发出触发脉冲上升沿，打开可控硅，并在相应半个周期结束前发触发脉冲下降沿，关断可控硅，为下个半周期触发做好准备。

Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock.

此外，CS的上升沿禁用设置时间内的I / O时钟和地址的货柜码头以及两个下降沿的内部系统时钟。

Data is latched on the rising edge of WE.

数据锁存对我们的上升沿。

After the UP and DN signals transition to a logic low, NAND gate 403 generates a rising edge in VIN, and pulse width generator 404 generates a rising edge in VOUT a delayed period of time later.

在UP和DN信号转换到逻辑低电平后，NAND门403在VIN中生成上升沿，且脉冲宽度发生器404在延迟时间段后在VOUT中生成上升沿。

Error 22225: clock signal is used on both rising edge and falling edge.

如题所示，这是设计风格的问题。为了支持DFT，一般建议只使用时钟的上升沿进行时序处理。来看错误例子

Computer keyboard and microcontroller interface procedures using the rising edge trigger interrupt service procedures, falling edge trig...

微机键盘和单片机的接口程序，采用了上升沿触发中断服务程序，下降沿触发中断服务程序。

Neither the killing of Mr Zarqawi nor any breakthrough on the political front will stop the insurgency and the fratricidal murders in their tracks.

在对危险的南部地区访问时，他斥责什叶派民兵领导人对中央集权的挑衅行为。

In fact,I've got him on the satellite mobile right now.

实际上 我们已接通卫星可视电话了