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read-only memory相关的网络例句

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与 read-only memory 相关的网络例句 [注:此内容来源于网络,仅供参考]

Long int readData(Buffer * pBuffer,/* pointer to the abstract buffer */ byte * pOutput,/* pointer to the output byte array */ long int offset,/* offset of the output byte array */ long int arrayLength /* size of available output byte array */){ while (there is something more to read and there is room for output){ read from the first memory block; if (the first memory block is empty){ delete the first memory block from the linked list and free its memory

在 清单 5 中,该函数销毁性地从 pBuffer 所指向的抽象缓冲区最多读取 arrayLength 个前导字节,并在内存块变为空时从链表中删除它们,然后返回成功读取的字节数目。如果需要,您可以实现一个类似 readData 的函数来允许非销毁性的读取。实现一个函数来返回当前存储在抽象缓冲区中的字节数目,这样可能会带来好处。清单 6。返回抽象缓冲区中的字节数目

If the disk is infected with the virus, the memory is read the first part of the virus program, it has been modified after the control of the size of memory space available in high-end memory think of a region, and moved to the first part of the area, and then read on the disk "bad cluster" in the second part of the first part and to put together, so that all proceedings on the presence of the virus in memory of the high-end, and then modify the interrupt vector INT13H or other interrupt vector to the high-end virus program, then you can read the original boot memory and the control over to it to complete the system startup.

如果是染上病毒的盘,读到内存的是病毒程序的第一部分,它得到控制权后修改内存可用空间的大小,在内存高端辟出一块区域,并把第一部分移至该区,接着读入放在磁盘"坏簇"中的第二部分,并和第一部分拼起来,使病毒程序全部驻留在内存的高端,然后修改INT13H的中断向量或其它中断向量,使其向高端的病毒程序,这时即可把原引导程序读到内存中,并把控制权交给它以完成系统的启动。

It has a microcontroller peripheral devices are connected to high-speed bus connections within the connection interface and memory card connection interface, the micro-controller memory card interface, high speed bus interface to connect external devices and virtual within the integrated drive electronics interface module, and the virtual integrated drive electronics interface module includes an integrated drive electronics interface to the virtual host and virtual device side, and when the host side of the card reader connected to the memory card storage or read the instructions issued, the command will be sent to Xuni integrated Shi-driven electronic interface module, and in which the instruction to complete, while the memory card of the information on the transmission to achieve high speed Waiwei components provided within the connecting bus transfer rate, and the host will think that reader is integrated drive electronics interface devices, not just within the high-speed peripheral devices connected bus devices.

其具有微控制器分别连接有高速外围元件内连接总线连接接口及存储卡连接接口,而微控制器具有存储卡接口、高速外围元件内连接总线接口及虚拟整合式驱动电子接口模块,且虚拟整合式驱动电子接口模块包括有整合式驱动电子接口的虚拟主控端及虚拟装置端,而当主机端对读卡机所连接的存储卡下达储存或读取的指令时,该指令会传送至虚拟整合式驱动电子接口模块,并在其中将指令完成,而存储卡内的资料于传输时可达到高速外围元件内连接总线所提供的传输速率,且主控端会认为读卡机为整合式驱动电子接口装置,而非单纯的高速外围元件内连接总线装置。

To imagine such a situation, when you more than the amount of memory, and run a relatively large-scale process, will inevitably lead to a sharp reduction in the number of physical memory, and in this case the so-called "optimization software," the beginning of smart aleck, the data memory for paging to the hard drive, and the procedures needed for the operation of the data, which may have led to at the same time, the "optimization of software" tried to data paging to the hard disk, and the operating system attempts to read data from the hard disk into memory, a very large increase in hard drive read and write.

想象这种情况,当你内存数量不多,而又运行了比较大型的程序后,必然导致物理内存数急剧减少,而在这种情况下所谓的"优化软件"开始自作聪明,把占用内存的数据往硬盘上进行分页,而程序的运行需要这些数据,这可能导致了在同一时间内,"优化软件"试图将数据分页到硬盘,而操作系统试图将数据从硬盘读取到内存,极大增加了硬盘的读写。

C Supports both Firmware Hub and LPC Memory Read and Write Cycles Auto-detection of FWH and LPC Memory Cycles C Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets C Can Be Used as LPC Flash for Non-Intel Chipsets Flexible, Optimized Sectoring for BIOS Applications C 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector, Three 64-Kbyte Sectors C Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing Two Configurable Interfaces C FWH/LPC Interface for In-System Operation C Address/Address Multiplexed Interface for Programming during Manufacturing FWH/LPC Interface C Operates with the 33 MHz PCI Bus Clock C 5-signal Communication Interface Supporting Byte Reads and Writes C Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors C Five General-purpose Input Pins for System Design Flexibility C Identification Pins for Multiple Device Selection C Sector Locking Registers for Individual Sector Read and Write Protection A/A Mux Interface C 11-pin Multiplexed Address and 8-pin Data Interface C Facilitates Fast In-System or Out-of-System Programming Single Voltage Operation C 3.0V to 3.6V Supply Voltage for Read and Write Operations Industry-Standard Package Options C 32-lead PLCC C 40-lead TSOP

0第0页,本页显示记录0-0,共0条记录分0页显示C支持两种固件中心和LPC内存读取和写入周期自动的FWH和LPC的记忆圈C检测可以用于英特尔8xx系列,E7xxx,E8xxx系列芯片组和C可以用作FWH与至于非英特尔芯片组的BIOS应用柔性优化扇区开放16字节热门引导扇区,两个8 - Kbyte的,一个32字节部门,3个64 - Kbyte的C或存储阵列,线性预测编码闪光可分为四个统一为两个可配置的接口擦除的FWH / LPC接口为64 - Kbyte的行业,系统运行C地址/地址多路复用在制造过程中用于编程接口的FWH /线性预测编码界面C与33 MHz的PCI总线时钟 5信号通信接口进行操作,支持字节读取和写入引导扇区的顶部和WP C两硬件写保护引脚:任务型为所有其他部门 5个通用输入的系统设计的灵活性识别的多种设备选型部门登记销锁定为个别部门读取和写保护的A /阿复用界面C 11引脚复用引脚地址和8引脚的数据界面C促进快速系统内或外的系统编程的单电压3.0V至3.6V的操作供应的读取和写入操作业界标准的封装选项电压 32 -引脚PLCC 40引脚的TSOP

The most important weakness of the Turing machine in comparison real computers is that its memory is not accessible immediately: in order to read a distant memory cell, all intermediate cells must also be read.

最重要的弱点,图灵机相比,真正的电脑,其内存是无法访问的立即:为了宣读了遥远的记忆细胞,所有的中间细胞还必须阅读。

The high speed multiplex first-in first-out storage structure includes at least two memory unit arrays, one integrated decoder circuit between the two memory unit arrays, one write-in control circuit over the decoder circuit, one read-out control circuit below the decoder circuit, two data buffers on the two memory unit arrays separately, two multiplex circuits and two output circuits below the two memory unit arrays separately, and one write-1 clock buffer and one read-out clock buffer over and below the decoder circuit separtely.

一种高速多路先进先出存储器结构,包括一至少两存储单元阵列、一位于至少两存储单元阵列中间的整体解码电路、分别位于整体解码电路的上下的一写入控制电路及一读出控制电路、分别位于至少两存储单元阵列上的两数据输入缓冲器以及依序位于两存储单元阵列下的两多工电路及两输出电路,在整体解码电路的上下分别设置一写入时钟缓冲器及一读出时钟缓冲器。

Read and write of flash disk as USB host.According to the request of this subject, the system hardware and software for the slave device, and the communication interface to the master PC are developed. Detailed works are as follows: in order to implement the measurement principle in the system, flow-liquid levelmethod is used;velocity of flow is measured through rotor Kinemometer;water level is surveyedvia RS485 interface and pressure sensor;the C8051F060 chip which is in high performance andintegration, produced by Silicon Laboratories Company as master chip is used to capture and measure the width of impulses, so singals of flow velocity are collected and disposed;the 4×4 matrix keyboard and LCD are used in the part of man-machine interface which are easy to input, legible to read, various to display, comfy to be accepted and plain to show measure and inquiry results;FRAM memory FM3164 is used to carry out the non-volatile memory of data and accurate real-time clock.;SL811HST chip is used as USB host which can read and write flash disk,thereby a kind of adscititious mass storage is accomplished .

根据研制任务的要求,课题期间主要完成了下位机系统硬件和软件,设计了与上位机的通讯界面,所做的具体工作包括:测量原理在系统中的实现,采用了流速—水位计算法,通过旋桨式流速仪来测量流速,通过RS485接口与压力变送器通讯测量水位;主控制芯片采用了Silicon Laboratories公司的高性能、高集成度C8051F060芯片,利用其捕捉测脉宽的特性,实现了流速信号的采集和处理;人机接口部分采用了4×4矩阵键盘和LCD显示,输入方便,读数清晰,显示多样化,信息量大,易于被用户接受,更直观地显示测量及查询结果;通过采用铁电存储器FM3164实现了数据的非易失性存储和精确的实时时钟;通过采用SL811HST芯片,实现了USB主机的功能,可读写U盘,从而实现了单片机的外挂式海量存储。

A frame image of a video frequency sequence is read into a postpositional memory zone, and staring position and size information of a tracked object is obtained in the frame, then distribution statistical information of a target signature is extracted to build a gauss mixed model as an object template, a mean vector and a covariance matrix in gauss mixed distribution are used to describe the position and the size of the object, then the next frame image of the video frequency sequence is read into the postpositional memory zone. In a new frame video frequency image, a parameter estimation method is used to obtain object gauss mized model parameters in the current frame in iterative computation and find candidate template similar to the object template, and the final model parameters obtained in iteration are used to update the tracking window for realizing self-adaption of the tracked window.

将视频序列的一帧图像读入缓存区,获得该帧中被跟踪目标的初始位置和尺寸信息,然后提取目标特征的分布统计信息建立高斯混合模型作为目标模板,用高斯混合分布的均值向量和协方差矩阵描述目标的位置和尺寸,再将视频序列下一帧图像读入缓存区,在新一帧视频图像中利用参数估计方法迭代计算当前帧中目标高斯混合模型参数找到与目标模板最相似的候选模板,利用迭代得到的最终模型参数更新跟踪窗口实现跟踪窗宽的自适应。

The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构,采用多元线性回归方法分析SRAM宏单元性能指标,采用解析方法分析控制电路延时,结合以上这两种方法建立嵌入式SRAM性能混合模型,该模型清晰划分两种建模方法的各自适用范围,提高了模型精度;其次以该混合模型为基础建立存储体性能目标函数,采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构,使之达到最优设计;最后综合考虑面积、功耗、速度以及可靠性等因素,建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程,分析了&读破坏&和&写破坏&的晶体管尺寸约束,优化了6-T存储单元尺寸,提高了嵌入式SRAM性能。

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