查询词典 pipelined

This method has the advantage of TCP handoff's high performance,and supports P-HTTP and pipelined requests.

该方法具有TCP迁移高性能的优点，且能很好地支持P-HTTP和流水线请求。

Contents include basic computer architecture design, microprogramming control design, data path design, pipelined and vector processing design, multiprocessor design, reduced instruction set computers design… etc.

内容包含：基本计算机组织与设计，微程式控制设计，资料路径设计，管线与向量处理设计，多处理器系统设计，精简指令集电脑设计等。

There are a number of hidden contributions to this work, beyond the construction of a fully verified, optimizing compiler: The compiler was built in a modular, pipelined fashion as a series of translations between well-specified intermediate languages, making it possible to add new optimizations or reuse components for other projects.

除了构造一个完全经过验证的优化编译器之外，这项工作还有一些更多贡献：采用了模块化、管道－过滤器设计模式，将整个编译器划分为一系列规范良好的中间语言之间变换的模块，这为加入新优化算法或者是在别的项目中重用这些模块提供了可能。

The measured object can be found within a few milliseconds in the raster-scan image. 4 . Two lines delay for the processed image is implemented using two 128×8 shift registers with the configurable logic block in FPGA. A new fully pipelined bit parallel hardware architecture for Sobel edge detection is implemented with FPGA. Furthermore, it takes no more than 2ms to complete the edge detection of an image with 128×128 pixels.

视觉检测信号的前端处理技术 1、系统地分析了视觉检测算法层次性特点和计算特点，提出了提高视觉检测信号处理速度的基本方案：采用前端处理系统，自动识别被测物体在获取图像中的位置，并将真正有用的被测物体的边缘坐标值，提供给计算机，作进一步的高精度处理； 2、系统研究了实时图像硬件处理的设计基本方法，提出了基于FPGA的视觉检测信号的低级处理算法硬件实现模块化模型； 3、提出了一种新的基于FPGA的模板匹配并行模块化结构，解决了二维图像处理高带宽要求，在几毫秒内就可以在按扫描顺序输入图像中找到检测目标物体的位置； 4、采用FPGA内部的可配置逻辑块实现了128×8移位寄存器的设计，解决了大容量移位寄存器与FPGA内部寄存器数量之间的矛盾，实现了两行图像的延迟。

This article discusses fix quantity connection between quaternion non-linearity continuous function △ERR_ and △ERR_ in the reference literature~([1]),and its decisive effect on distributing evolvement disperse drop field in the error ratio function ERR_(100nm%)λ_(centreT,n,thus paves the way for the function degree of redundancy of Pipelined-Flash A/D.

本文讨论参考文献[1]中两类四元非线性连续函数△ERRdn与△ERRdj之间的定量关系，对误差比率函数ERR100nm%离散点域分布演变所起的决定性作用。

The ADC is pipelined, including a single-input/difference-output sample/hold circuit and nine stage subcircuits. The preceding eight stages are 1.5bits/stage, and the last stage consists of two comparators. Every input sample is converted into 18 bits binary signals, and these binary signals are converted into 10 bits binary signals through digital correction circuit.

模数转换电路采用流水线式的结构，包括具有单端输入/差动输出功能的采样保持电路和九级的子电路，前八级子电路使用1.5位/级的结构，最后一级使用两个比较器实现，每个输入值被转换为18位的二进制代码，通过数字纠正技术最终实现10位的输出，按照前端电路的应用要求，这个模数转换器实现1.33MHz的采样速率。

We propose the mirror-image decomposition of dependence graph to solve the parallelization of self-dependent Field-Loops, which has been an unsolvable problem in traditional methods, and realize both the wavefront and pipelined execution of selfdependent Field-Loops.

本文提出的相关图镜像分解技术解决了传统技术无法处理的自相关场循环的并行化问题，成功实现了自相关场循环的波前并行和流水并行。

Compressible ; multi-scales ; super compact symmetric finite difference scheme ; parallel algorithm ; block pipelined method

用分块流水线方法设计了超紧致差分格式的并行算法，进行数值实验及并行性能分析。

Tejas was a troubled super-pipelined design that would succeed Prescott, but was cancelled after the power consumption and heat dissipation problems became known.

Tejas是Prescott的后继，同样采用了麻烦的超长流水线设计，而后因为功耗和散热问题暴露之后被取消。

The principles of CORDIC is introduced in this paper first. Then a new pipelined architecture to realize discrete trigonometric function generator in high speed and accuracy is described.

介绍了CORDIC的基本原理，提出了一种利用流水线CORDIC结构来实现高速度精度的三角函数发生器的设计。

The labia have now been sutured together almost completely.The drains and the Foley catheter come out at the top.

此刻阴唇已经几乎完全的缝在一起了，排除多余淤血体液的管子和Foley导管从顶端冒出来。

To get the business done, I suggest we split the difference in price.

为了做成这笔生意，我建议我们在价格上大家各让一半。