查询词典 pipeline architecture

The purpose and significance of the thesis are clarified and the framework of the thesis is brought out. Chapter 2 gives an overall and systematical survey of the development of parallel processing systems. The computing model, program behavior, architecture selection and the performance of parallel processing on four classes of parallel processing systems—multi-processor, SIMD computer, pipeline computer and VLSI array processor are elaborated.

由此，本文的主要内容安排如下：第一章对自适应光学系统及其实现的意义作了简要描述，并着重评述了自适应光学系统的关键部件—波前图像处理机的研究概况，同时阐述了本文的研究目的和意义，进而给出了全文的基本结构框架。

The algorithm is modified. The binary arithmetic codec used in JPEG2000 system based on pipeline architecture is presented.

并且采用了流水线的结构，分别设计了基于优化算法的MQ编码器和解码器，从而大大改进了编码和解码的效率。

This paper brought forward some new design schemes based on the principle and signal processing algorithm of velocity detector, and introduced the hardware construction of the velocity detector based on Depolarizer and S3C2410A microprocessor. The high-efficient ARM program of radical 4-FFT was designed according to the architecture characters of ARM core. In the process of code designing, the instruction scheduling and register allocation were controlled subtly, and the fixed-point number's storage format and computing method of float number were provided. Barrel shifter and 5-lever pipeline were fully utilized and the pipeline interlock was avoided.

针对多普勒测速仪的基本原理和信号处理算法提出了新的设计方案，介绍了由多普勒收发前端和三星S3C2410A处理器构成的测速仪的硬件结构；并结合ARM内核设计特点实现了基4时间抽取快速傅里叶变换算法，针对大多数ARM处理器硬件上不支持浮点运算，提出了把浮点数以定点数格式存储和计算的方法，充分利用桶型移位器和5级流水线，避免了流水线互锁问题。

It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.

特别是流水线结构使得FFT处理器在进行不同点数的FFT计算时可以通过对模块级数的控制很容易的实现。

It's easy to implement the scalable FFT based on multilevel pipeline processing architecture in FPGA/CPLD.

特别是多级流水线处理的FFT结构使得基于CPLD/FPGA器件的FFT处理器完成不同点数的FFT计算时可以通过增减模块级数很容易地实现。

For the partial products generation, the novel method of Booth encoding combined with partial products generating is put up, which can directly map the multiplicand and multiplicator to partition products without generating the BOOTH encoding results. For the optimization of Wallace tree adding, the series formulas of full-adder and 4-2 Compressor realization are introduced to guidance the selection. For the non-bias round, forwarding round disposal in Wallace tree method is brought forward to avoid the final multi-bit adder. Also, the idea of delay-oriented partition of the MAC frame is put up to achieve the perfect match with multi-pipeline DSP architecture.

提出了一种构建多模式算法最小并集的MAC通用结构思想与一种划分MAC通用结构以适应多流水级DSP处理器设计的通用MAC设计方法；对于BOOTH编码和部分积产生，提出了直接建立被乘数与部分积的多路选择映射关系的BOOTH编码和部分积联合产生方法；对于最优Wallace树型加法实现，提出了全加器和4-2 compressor电路实现Wallace树加法所需的关键加法路径级数公式以指导实现选择；对于无偏舍入处理，提出了在Wallace树处理舍入问题的舍入运算前置方法；提出了以时延为导向的MAC各部分单元组合与流水线匹配具体方法。

Designing a VLIW signal processor architecture URPR-1 based on URPR approach, in which pipeline register file is adopted to provide effective hardware support for optimizing compiler.(3) Proposing a phase-coupled optimizing compilation technique, two-level software pipelining.

作者根据URPR-1体系结构的特点，提出一种新的资源分配和代码优化两阶段相结合的优化编译技术—两级软件流水，设计和实现了采用该技术的优化编译器原型。

Therefore,through the Geodatabase data model quoted by ArcGIS,the authors discussed the pipeline data organization and presented the system frameworks according to different requirements of application.The whole system design and function realization are accomplished by the combination of B/S and C/S architecture,which solved the problems such as management,application and dynamic ruled data-update of underground pipelines information.Meanwhile,the referenced scheme and basic idea for system construction of underground pipelines are provided in the paper.

为此，利用ArcGIS引入的Geodatabase数据模型，探讨数据的组织形式，根据不同的应用需求提出系统的框架结构，采用B/S和C/S架构相结合方式进行系统总体设计和功能实现，解决了地下管线信息管理、应用和法规保证的动态更新等问题，为城市地下管线的系统建设提供了借鉴方案和基本思路。

The pipelined CORDIC architecture is very suitable for FFT butterfly operation because of its high throughput and regularity, but it will consume lots of resources,this article presents an improved architecture of CORDIC pipeline,starting with the property that the FFT rotary factor is fixed but not arbitrary,and according to the mapping between the basic rotational angle of CORDIC and scale factor and the rule for transform among the scale factors.On the condition that the velocity of FFT butterfly operati...

CORDIC流水线结构因其高吞吐率及规整性，而很适合于FFT蝶形运算，但其缺点是耗资源多，本文从FFT中旋转因子固定不任意的特点出发，根据CORDIC基本旋转角度与缩放因子的对应关系和缩放因子之间的转换规律，对CORDIC流水线结构进行了改进，在蝶形运算速度不变的情况下，进一步减少所耗资源，在字长为16位的FFT中，每个旋转因子可用25位的控制序列来替代，从而使每个旋转因子的存储空间由32位减少到25位。

This was followed by the highly successful Matrox Image Series in 1989, which raised performance standards with its new hardware pipeline architecture and MIL software library.

其次是非常成功的Matrox图像序列在1989年，这引起了性能标准的新的硬件架构和MIL管道的软件库。

The labia have now been sutured together almost completely.The drains and the Foley catheter come out at the top.

此刻阴唇已经几乎完全的缝在一起了，排除多余淤血体液的管子和Foley导管从顶端冒出来。

To get the business done, I suggest we split the difference in price.

为了做成这笔生意，我建议我们在价格上大家各让一半。