查询词典 parallel lines

The data lines are parallel to each other and intersect with the scan lines to demarcate pixel regions.

资料线彼此平行排列并与扫描线相交以围出的多个画素区域。

I've stitched Euclid's parallel postulate on to the surface. And the lines look curved. But look, I can prove to you that they're straight because I can take any one of these lines, and I can fold along it. It's a straight line.

我将欧几里德平行公设编织到表面上，这些线条看起来是弯曲的，但你看，我可以向你证明它们是直线；因为我可以拿起任何一条线，我可以沿线折叠，这是一条直线。

In an uniform field, the lines of force are straight parallel, and uniformly spaced.

在匀强电场中，电力线是平行的直线，其间隔是均匀的。

Transmission line loadings may be affected directly by the power input to the line from connected generating units or changes in parallel paths that may be changed by placing other lines into or removing them from service.

输电线路的负荷可直接受到来自所联接发电机组功率输入的影响，或受到并联运行线路变化的影响，这种变化可以是其它并联线路的投入或退出。

Bit Single Scan Display Type A 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred.

位单扫描显示方式 4 位单扫描采用 4 位并行数据线将行数据一次连续移出，直到整个帧的数据被移出为止。

Bit Single Scan Display Type An 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred.

位单扫描显示方式 8 位单扫描采用 8 位并行数据线将行数据一次连续移出，直到整个帧的数据被移出为止。

The classical theorists resemble Euclidean geometers in a non-Euclidean world who, discovering that in experience straight lines apparently parallel often meet, rebuke the lines for not keeping straight--as the only remedy for the unfortunate collisions which are occurring.

古典学派的理论家们很像置身于非欧几何世界中的欧几里德几何学家们，一旦发现在日常经验中两条显然平行的直线经常会相交，他们就会指责说线没有保持平直——这被看作是解决两条线发生不幸冲撞的唯一办法。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Main PPR, ABS, PEX Pipe Production Line, PVC, HDPE gas pipe production line, large-caliber hollow-wall winding pipe production line, silicon core pipe production line, steel-plastic composite, medical tube, nylon tube production line, PVC foam core pipe, with spiral pipe production line, posts and telecommunications perforated pipe production line, double-wall corrugated pipe, spiral pipe production line, peroxides, cross-linked polyethylene, pipe production lines, two-pipe extrusion production line, plastic board material production line, plastic foam picture frame-type material production line, SJYF plastic profile extrusion production lines, blow molding Blow Molding Machines, Single Screw eager, cold-cut granulator unit, with the parallel twin-screw extruder, SJSZ conical twin-screw plastic extruder, SJ single screw extruder, SRL-Z series mixing unit, SHR series high speed mixer, auxiliary products sold nationwide and exported to Southeast Asia more than 10 countries and regions.

主要有PPR、ABS、PEX管材生产线、PVC、HDPE燃气管生产线、大口径中空壁缠绕管生产线、硅芯管生产线、、钢塑复合、医用管、尼龙管生产线、PVC芯层发泡管、内螺旋管生产线、邮电通讯多孔管生产线、双壁波纹管、螺旋管生产线、过氧化物、交联聚乙烯、管材生产线、双管挤出生产线、塑料板材生产线、塑料发泡镜框型材生产线、SJYF塑料挤出异型材生产线、吹塑中空成型机、单螺杆热切、冷切造粒机组、同向平行双螺杆挤出机、SJSZ锥形双螺杆塑料挤出机、SJ单螺杆挤出机、SRL-Z系列混合机组、SHR系列高速混合机、辅机系列产品畅销全国并出口东南亚等十多个国家和地区。

It has been put forward that there exists single Ball point and double Ball points on the symmetrical connecting-rod curves of equilateral mechanisms.

从鲍尔点的形成原理出发，分析对称连杆曲线上鲍尔点的产生条件，提出等边机构的对称连杆曲线上有单鲍尔点和双鲍尔点。

The factory affiliated to the Group primarily manufactures multiple-purpose pincers, baking kits, knives, scissors, kitchenware, gardening tools and beauty care kits as well as other hardware tools, the annual production value of which reaches US$ 30 million dollars.

集团所属工厂主要生产多用钳、烤具、刀具、剪刀、厨具、花园工具、美容套等五金产品，年生产总值3000万美元，产品价廉物美、选料上乘、质量保证，深受国内外客户的青睐