查询词典 memory

2Spatial learning and memory:In the cued condition, the avoidance latency in the colzapine-exposed group was significantly shorter than the control group in the block 2(p.05),however there is no difference on block 3 between two groups;In the place condition,the clozapine-exposed group prrferred to finding the submerged platform in the serial blocks(P.01);in reversal condition,the filial rats exposed the clozapine had no advantage on finding out the submerged platform in block2,3,4 except of the block l(p.01),the further statistic analysis reminded that it is just the first trial that the filial rats in clozapine-exposed group had the advantage to find out the submerged platform in reversal condition (F=4.86, PO.01).it isimplicated that the clozapine exposed in the gestation lead to the improvement on the acquiry and consolidation.however the acquired memory seems not to be maintained.

OI；提示用药组大鼠的子代记忆巩固能力较对照组好；固定平台再认定位实验中，用药组大鼠的子代首轮寻找平台的潜伏期较对照组明显缩短(F一巧。04，P 。01)，以后数轮成绩没有差别。进一步的统计显示，氯氮平孕期使用组大鼠在再认阶段仅仅是首个方向更快的发现平台(F二486，P.01)，提示氯氮平孕期使用提高了记忆的获取，但这种已经获取的记忆优势并没有得到保持。

Thermochemical Hole Burning memory uses the STM heating effect to induce a localized thermochemical decomposition of Charge Transfer Complexes, evolving the low-boiling point donor component and creating nanometer-sized holes on the crystal surface. In this thesis, we focus our research on the material synthesis and storage mechanism of THB memory.

热化学烧孔(Thermochemical Hole Burning，THB)技术是基于STM的超高密度信息存储技术，它利用STM针尖产生的隧道电流或场发射电流的焦耳热效应，诱导二元电荷转移复合物材料发生局域热化学气化分解反应，使低沸点组分从样品表面逸出，形成纳米尺度的信息孔。

From this we can get the root of the memory and art idol.The second chapter is a short discussion about the memory.

第二章是对记忆的一个简要论述，指出记忆所具有的对话性质和反排除功能。

Some psychologists believe that the root of most memory problems in old age is a diminished ability to control multiple pieces of information in working memory simultaneously.

一些心理学家认为老年人多数的记忆问题的根源是处理复杂信息的能力降低。

However, anti-plug memory after burning is not necessarily the end-of-life, the majority of normal use or because of how memory power supply and ground root, anti-plug is often because the local power supply is the ground and in the connected to pass, so as long as this power will be the role of a period of short-circuit ground wire from burning, and other ground and the chip has not been destroyed.

不过，内存条反插烧毁后并不是一定就报废了，多数还是能够正常使用的，这是因为内存条有多根供电和地线，反插时往往是因为局部的地线把电源正和地相连通，所以只要加电就会把这一段起短路作用的地线烧毁，而其他地线和芯片却没有被破坏。

There is a close relationship between monoamines and learning and memory. NE and dopamine are believed to have a role in facilitation of memory. For this, an observation of clausenamide on monoamines and their metabolites as well as monoamine oxidase B activity was carried out.

目前认为脑内单胺类递质的变化与学习记忆密切相关，其中DA，NE的增加有助于学习记忆的形成，为了探讨黄皮酰胺的促智作用机制，我们首先研究了黄皮酰胺对小鼠脑内单胺类递质及其代谢产物和单胺氧化酶的影响。

At very fast 100 us and low +/- 9 V P/E, good memory device integrity of 2.8 V initial memory window and large ten-year extrapolated retention of 1.8 V at 85oC or 1.5 V at 125oC are obtained in SiO2/Hf0.3N0.2O0.5/HfLaON/TaN MONOS device. Such excellent 85~125oC retention with small decay rate, at only 2.9 nm thin tunnel SiO2, is possible by tuning Hf0.3N0.2O0.5 trap energy deep into Si forbidden bandgap close to midgap.

在快速(100毫秒)和低电压(9伏)的操作条件之下，可得到2.8伏的记忆视窗；在85oC 和125oC环境下由外插法所得的十年资料储存能力，其记忆视窗仍有1.8伏和1.5伏，由於我们调整高含氮量氮氧化铪的捕陷能阶深入至靠近矽中间能带的禁止能带中，才能在仅2.9奈米穿遂氧化层的MONOS元件中，拥有如此突出的资料储存能力。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Unlike the popular method of reconstructing public memory in contemporary art practice, this series of Wang Yins works has developed from personal experience and memory.

和当代艺术中那种重塑公共记忆的流行做法很不相同，王音的这一批作品大都是从个人经验和记忆入手。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失