查询词典 memory-chip

Read only memory: Computer memory supplied as a chip inside the computer and which cannot be altered.

唯读贮记器：用者不能更改的电脑贮记元件，它以晶片形式装置于电脑内。

This address is mapped by the hardware to a certain read-only, persistent memory chip that is often called Read-Only Memory.

这个地址中的代码是由硬件将ROM芯片中的程序映射而来的。

ROM(Read-Only Memory) is a memory chip that only can be read and used; that is , it cannot be modified

修改。 ROM是一种只能读取，不能修改的存储器。

The third part of paper introduces the principle of the wireless monitoring system briefly, and introduces the microprocessor, data memory, data memory, serial interface circuit, AD chip, temperature sensor, manostat detailedly.

论文第三部分简单介绍了无线监控系统的原理，重点介绍了无线监控单元用到的微处理器、数据存储器、串口电路、摸数转换器、温度传感器、稳压器的特性及其接口电路。

However, anti-plug memory after burning is not necessarily the end-of-life, the majority of normal use or because of how memory power supply and ground root, anti-plug is often because the local power supply is the ground and in the connected to pass, so as long as this power will be the role of a period of short-circuit ground wire from burning, and other ground and the chip has not been destroyed.

不过，内存条反插烧毁后并不是一定就报废了，多数还是能够正常使用的，这是因为内存条有多根供电和地线，反插时往往是因为局部的地线把电源正和地相连通，所以只要加电就会把这一段起短路作用的地线烧毁，而其他地线和芯片却没有被破坏。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Firstly it introduces relevant technical developments and trends, the task background and significance of the study, then analyzes hardware circuit of using image sensor as images collected, and utilizes the SAA7113 chip to deal with video image beforehand, SAA7113 lets the output of standard digital video signals to storage in FIFO memory, and decodes clock signals, Highlighted microprocessor control external circuit design of false coin and counting, and DSP control external circuit design, such as memory expand ect;Finally analyses CPLD as logic controller to control the logic and scheduling of some part ,and gives the undee emluator of some logic circuit.

文章首先阐述人民币智能分捡器相关技术的发展状况、发展趋势以及课题背景与研究意义；然后设计了利用图像传感器采集人民币图像输出模拟视频信号的硬件电路，以及利用视频解码芯片(SAA7113)对模拟视频图像进行预处理，SAA7113输出的标准数字视频信号存入FIFO存储器，同时还解码输出场、行同步信号、像素时钟信号送入CPLD等部分电路；重点设计了单片机控制验钞、点钞等外围电路，以及DSP控制的外围电路，如存储器的扩展等部分；最后完成CPLD对部分器件的逻辑和时序控制设计，并对逻辑电路的功能进行仿真，仿真结果令人满意。

By default, 15KB are assigned as Scratch-Pad memory to the corresponding TU. The remaining 15KB of all 160 TUs create the 2400KB SRAM memory, which is shared among all TUs of the chip.

默认情况下 15KB分配给指定线程单元充当分块缓存，剩下的15KB/片组成160个线程单元共享的2400KB高速缓存，在启动时，指定给每线程单元的分块缓存大小可以重新配置。

Description : in the computer system, in order to increase the utilization rate of survival, often auxiliary memory as a main memory expansion, multi-channel operation run the logic address space can exceed the sum of the absolute main memory address space.

简介：在计算机系统中，为了提高主存利用率，往往把辅助存储器作为主存储器的扩充，使多道运行的作业的全部逻辑地址空间总和可以超出主存的绝对地址空间。

The work of this paper is as follows: 1. Looking back the progressing history of the linear motor, introducing the features of the elevator driven by linear induction motor, radicating the topic of this paper "the digital frequency variable control of the elevator bi-side direct driven by linear induction motor". The research of this paper covers the conventional VVVF control, space vector based VVVF control, vector control and DTC.

本文主要开展了以下几个方面的工作： 1 回顾了直线电机发展历史，电机的驱动技术演变，特别是针对直线电机的驱动，简要介绍了直线感应电机驱动电梯的优点和不同结构类型，对传统的v／f控制，基于空间矢量法的v／f控制，矢量控制，和基于电压空间矢量的直接转矩控制进行了比较，确立了本课题的研究主题：直线感应电机双边直推式驱动电梯的全数字变频控制。

The article combines with the treatment of a superficial civil air defense work to introduce how the grouting method to improve the performance of the backfill soil.

文章从治理漂浮人防工事的角度提出了注浆技术在改善回填土性质方面的应用，并详细阐述了注浆技术的施工流程。