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First, a new type of competitive associative memory model ...

首先提出的是对传统联想记忆模型改进的竞争联想记忆模型和它的扩展模型。

But some details about atomicity are available in the Go Memory Model specification.

但是一些关于原子化的细节在Go 的内存模型规范里有说明。

Central Executive plays a key role in response inhibition,episodic buffer proposed in Baddeley new working memory model is where the feature binding happens.

4研究揭示了中央执行系统在刺激特征联合的反应抑制中的功能,支持由Baddeley(2000)新工作记忆模型中提出的情景缓冲器的假设。

The working memory model established by Baddeley and Hitch (1974) consist of central executive、 Visuo-spatial sketch pad and Phonological loop. Central executive play a crucial role that making our attention on the related information processing, inhibiting irrelevant information, responsible for the information to transform among various processes in the complex tasks.

Baddeley和Hitch提出的工作记忆模型由中央执行系统、视空间模版、语音环等成分构成,中枢执行系统具有核心控制作用,它保证大脑将注意集中在相关信息及加工过程上,而对无关信息进行抑制,负责在复杂任务中的各个不同过程间进行转换,对工作记忆中的内容进行监控等。

The preliminary analysis and computer simulation show that the model has some capabilities that conventional associative memory model do not have, such as it can response to same input with different outputs under different conditions, and response to different inputs with same output under different conditions.

通过初步分析和计算机模拟,证明本模型具有一般联想记忆模型所未有的一些新的特性,如可以在不同条件下,对同一输入有不同的反应。对同一输入,在不同的条件下,又可以有相同的反应。

Under Win32, there's no "near" or "far" pointer, just pointer because of the new FLAT memory model.

因为 win32 中内存模式是平坦模式。没有段内和段间之分。

And make a long memory model. Using this model to predict, draw a very accurate results.

并用所建的模型进行预测,得出了很精确的结果。

At the same time, inductiveness and evaluation of the two main implicit memory model: multiple memory system theory and migration appropriate processing theory, as well as their problems.

同时,归纳与评价了两种主要的内隐记忆模型:多重记忆系统理论和迁移恰当加工理论,以及他们存在的问题。

Was based on the memory model form that offer to build hardware architecture, come true on FPGA, the test makes clear as a result, with direct visit advocate memory photograph is visited than be in put rose to arrive severalfold on speed about a hundred times.

基于提出的存储模型构建了硬件体系结构,并在FPGA上实现,测试结果表明,和直接访问主存储器相比在访存速度上提高了几倍到上百倍。

In order to achieve a better application effect of Scratch-Pad Memory, it,s appropriate to construct a proper SPM's performance and power-consumption model to guide the compiling optimization process.

摘要为了获得SPM(Scratch-Pad Memory)部件最佳的使用效果,需要合适的SPM性能和功耗模型来指导编译优化过程。

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